EP910ILC-50 vs EP910LC-40H 비교
다음의 상세 나란히 비교: EP910ILC-50 제조: Intel 및 EP910LC-40H 제조: Altera. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.
사양 비교
| 파라미터 | EP910ILC-50 | EP910LC-40H |
|---|---|---|
| 브랜드 | Intel | Altera |
| 카테고리 | FPGA & CPLD | FPGA & CPLD |
| 수명 주기 상태 | Obsolete | Obsolete |
| 재고 상태 | In Stock | In Stock |
| 단가 (USD) | $10.85 | $9.95 |
| Family | Altera Classic EPLD | Classic EPLD (EP910) |
| Macrocells | 24 | — |
| Usable Gates | 900 (typical) | 450 |
| Maximum Frequency | [DATA_NEEDED: fMAX value from datasheet] | — |
| Pin-to-Pin Delay (tpd) | 50 ns | — |
| Supply Voltage (VCC) | 5 V (typical) | 4.75 V to 5.25 V (5 V nominal) |
| User I/O Pins | 24 | — |
| Dedicated Input Pins | 12 | — |
| 패키지 | PLCC-44 (J-lead) | 40-pin Ceramic DIP (CDIP-40), JEDEC standard |
| 실장 유형 | Surface Mount (socket-compatible) | Through-Hole (THT) |
| Technology | CMOS EPROM, UV-erasable | CMOS, UV-erasable EPROM |
| 동작 온도 | 0C to +70C (commercial) | -40C to +85C (industrial) [DATA_NEEDED: confirm exact temp grade] |
| Programming Cycles | 100 (minimum) | — |
| Boundary Scan | IEEE 1149.1 JTAG (selected speed grades) | — |
| RoHS 상태 | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: not confirmed from datasheet - non-RoHS likely given vintage ceramic DIP] |
| Macro Cells | — | 24 |
| Logic Elements | — | 24 macro cells / expandable to 48 via expander terms |
| Propagation Delay (tPD) | — | 40 ns max |
| Supply Current (ICC) | — | Low-power CMOS, typical ICC < 100 mA |
| Speed Grade | — | -40 (40 ns tPD) |
| Programming Method | — | UV-erase + EPROM program, ~100 erase cycles |
| I/O Pins | — | [DATA_NEEDED: I/O count - datasheet indicates 36 user I/O typical] |