EP910LI-40 vs EP910LI44 비교
다음의 상세 나란히 비교: EP910LI-40 제조: Altera 및 EP910LI44 제조: Altera. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.
사양 비교
| 파라미터 | EP910LI-40 | EP910LI44 |
|---|---|---|
| 브랜드 | Altera | Altera |
| 카테고리 | FPGA & CPLD | FPGA & CPLD |
| 수명 주기 상태 | Obsolete | Obsolete |
| 재고 상태 | In Stock | In Stock |
| 단가 (USD) | $12.90 | $8.20 |
| Manufacturer | Altera (now Intel PSG) | — |
| Product Family | Classic EPLD - EP910 series | — |
| Device Type | Erasable Programmable Logic Device (EPLD) | — |
| Macrocells | 24 | 24 |
| Dedicated Inputs | 12 | 12 |
| I/O Pins | 24 bidirectional | — |
| Maximum Logic Inputs | 36 | 36 |
| Product Terms | 240 | — |
| Propagation Delay (tPD) | 40 ns | — |
| Technology | Low-power CMOS (L-suffix) | CMOS |
| 동작 온도 | -40C to +85C (industrial, I-suffix) | — |
| 패키지 | PLCC-44 (J-lead, windowed ceramic) | — |
| 실장 유형 | Surface Mount (socket-compatible) | Surface Mount (PLCC socket compatible) |
| Programmability | UV-erasable, JEDEC-standard algorithm | UV-erasable (windowed) or OTP |
| RoHS 상태 | Non-compliant (windowed ceramic PLCC, legacy) | non-compliant (original PLCC-44 lead finish) |
| Lifecycle | Obsolete - replaced by MAX 7000 / MAX II CPLD family | — |
| Family | — | Classic EPLD |
| Architecture | — | PAL-type, CMOS, One-Time-Programmable |
| Package Type | — | PLCC-44 (J-lead, surface mount) |
| Total Pins | — | 44 |
| Bidirectional I/O | — | 24 |
| Maximum Outputs | — | 24 |
| Flip-Flops | — | 24 |
| External Clocks | — | 2 |
| Maximum Propagation Delay | — | [DATA_NEEDED: tpd for unmarked speed grade; speed-grade suffix encodes value: -15 = 15 ns, -20 = 20 ns, -25 = 25 ns, -30 = 30 ns, -35 = 35 ns, -40 = 40 ns, -45 = 45 ns, -50 = 50 ns] |
| Supply Voltage (VCC) | — | 4.75 V to 5.25 V (commercial), 4.5 V to 5.5 V (industrial) |
| Operating Temperature (L grade) | — | -40 °C to +85 °C (industrial) |
| Programming Method | — | Altera Logic Programmer card / Data I/O / third-party EPROM programmers |