EPC16QC100II vs EPC16QC100-TAAC80 비교
다음의 상세 나란히 비교: EPC16QC100II 제조: Altera 및 EPC16QC100-TAAC80 제조: Altera. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.
사양 비교
| 파라미터 | EPC16QC100II | EPC16QC100-TAAC80 |
|---|---|---|
| 브랜드 | Altera | Altera |
| 카테고리 | Memory ICs | Memory ICs |
| 수명 주기 상태 | NRND | Obsolete |
| 재고 상태 | In Stock | In Stock |
| 단가 (USD) | $10.75 | $25.20 |
| 메모리 유형 | FPGA Configuration PROM (Flash-based) | Flash (non-volatile configuration) |
| Memory Density | 16 Mbit | 16 Mbit |
| Supported FPGA Families | APEX II, APEX 20K, Mercury, ACEX 1K, FLEX 10K, FLEX 8000, Cyclone | Stratix, APEX II, APEX 20K, Mercury, ACEX 1K, FLEX 10K |
| Configuration Mode | FPP / PSA (Fast Passive Parallel / Passive Serial Asynchronous) | — |
| Programmability | In-System Programmable via IEEE 1149.1 (JTAG) | — |
| Cascade Support | Yes (multi-PROM cascading supported) | — |
| Core Supply Voltage | 3.3 V | — |
| I/O Tolerance | 5 V tolerant configuration pins | — |
| 패키지 | 100-pin PQFP (Plastic Quad Flat Pack) | 100-pin PQFP (Plastic Quad Flat Pack), 20x14 mm |
| Package Dimensions | 20 mm x 14 mm, 0.5 mm pitch | — |
| Lead Finish | Matte Tin (lead-free) | — |
| 동작 온도 | -40C to +85C (Industrial) | -40C to +85C (industrial) |
| MSL 레벨 | 3 (per JEDEC J-STD-020) | — |
| RoHS 상태 | Compliant | — |
| Configuration Pins | DCLK, DATA[0..n], nCONFIG, nSTATUS, CONF_DONE, OE | — |
| Compression Support | Yes (reduces on-PROM footprint vs uncompressed bitstream) | — |
| Configuration Modes | — | FPP, PS, AS, JTAG |
| Data Compression | — | Yes (built-in, 30-55% file size reduction) |
| Supply Voltage (VCC) | — | 3.3 V |
| I/O Voltage Tolerance | — | 1.8 V / 2.5 V / 3.3 V / 5 V |
| JTAG Support | — | IEEE 1149.1 boundary scan, in-system programmable |
| Package Code | — | QC100 |
| Packaging Style | — | Tape and Reel (TAAC80 suffix) |
| Configuration Controller | — | Internal (integrated with flash array) |
| 핀 수 | — | 100 |
| 실장 유형 | — | Surface Mount |