EPF10K50EQI240-2N vs EPF10K50VQI240-2N 비교
다음의 상세 나란히 비교: EPF10K50EQI240-2N 제조: Intel 및 EPF10K50VQI240-2N 제조: Altera. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.
Intel
EPF10K50EQI240-2N - 50K-Gate FLEX 10KE FPGA, 240 PQFP | Intel / Altera
EPF10K50EQI240-2N ObsoleteAltera
EPF10K50VQI240-2N - FLEX 10K 50K-Gate FPGA, 240-PQFP, Industrial | Altera
EPF10K50VQI240-2N ⚠ 최종 구매사양 비교
| 파라미터 | EPF10K50EQI240-2N | EPF10K50VQI240-2N |
|---|---|---|
| 브랜드 | Intel | Altera |
| 카테고리 | FPGA & CPLD | FPGA & CPLD |
| 수명 주기 상태 | Obsolete | 최종 구매 |
| 재고 상태 | In Stock | In Stock |
| 단가 (USD) | $52.10 | $55.00 |
| Family | FLEX 10KE | FLEX 10K |
| Logic Elements / Cells | 2880 | — |
| Total RAM Bits | 40960 | 20480 |
| Number of LABs / CLBs | 360 | — |
| Maximum System Gates | 199000 | — |
| User I/O Pins | 189 | — |
| Number of I/O Banks | [DATA_NEEDED: I/O bank count] | — |
| Core Supply Voltage (VCCINT) | 2.5 V | — |
| I/O Supply Voltage (VCCIO) | MultiVolt 2.5 V / 3.3 V / 5.0 V | — |
| Internal Frequency (max) | 66.67 MHz | 125 MHz (per FindIC comparison data) |
| Propagation Delay (per LE) | 0.6 ns | — |
| Process Technology | 0.22 µm CMOS, SRAM-based | 0.42 um CMOS |
| Package Type | 240-pin PQFP / BQFP (FQFP, gull-wing) | — |
| 실장 유형 | Surface Mount (SMD/SMT) | Surface Mount |
| 동작 온도 | -40 °C to +85 °C (Industrial) | -40C to +85C (industrial, I-suffix) |
| Configuration Method | SRAM (volatile) — requires external EPC PROM | SRAM, serial EPROM (EPC1/EPC2) |
| Embedded Memory | Embedded Array Blocks (EABs), configurable as RAM/ROM/FIFO | — |
| Logic Family | CMOS | — |
| RoHS 상태 | unknown | [DATA_NEEDED: RoHS status] |
| Series | — | FLEX 10K |
| Logic Cells / Elements | — | 2880 |
| Typical Gates | — | 50000 |
| LAB/CLB Count | — | 360 |
| Number of I/O | — | 189 |
| Voltage - Supply | — | 5 V (VCCINT), 5 V / 3.3 V / 2.5 V (VCCIO via multiVolt I/O) |
| 패키지 / 케이스 | — | 240-BFQFP (PQFP, gull-wing) |
| 핀 수 | — | 240 |
| Package Code | — | FQFP / PQFP |
| Terminal Form | — | GULL WING |
| Propagation Delay | — | 0.6 ns (per digchip snippet) |
| In-System Programmable | — | Yes |
| PCI Compliance | — | PCI Local Bus Specification Revision 2.2 |
| Speed Grade | — | -2 (medium) |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |