EPF10K50VQC240-1N vs EPF10K50VQC240-2 비교
다음의 상세 나란히 비교: EPF10K50VQC240-1N 제조: Altera 및 EPF10K50VQC240-2 제조: Altera. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.
Altera
EPF10K50VQC240-1N - 50K-Gate FLEX-10K FPGA | Intel / Altera | 240-PQFP
EPF10K50VQC240-1N Obsolete
사양 비교
| 파라미터 | EPF10K50VQC240-1N | EPF10K50VQC240-2 |
|---|---|---|
| 브랜드 | Altera | Altera |
| 카테고리 | FPGA & CPLD | FPGA & CPLD |
| 수명 주기 상태 | Obsolete | Obsolete |
| 재고 상태 | In Stock | In Stock |
| 단가 (USD) | $11.50 | $28.75 |
| Manufacturer | Intel / Altera | — |
| Series | FLEX-10K | FLEX-10K |
| Typical Gates | 50,000 | — |
| Logic Elements / Cells | 2,880 | — |
| Total RAM Bits | 20,480 | — |
| Logic Array Blocks (LABs) | 360 | — |
| User I/Os | 189 | — |
| Number of I/O Banks | [DATA_NEEDED: number of I/O banks] | — |
| 공급 전압 | 3.0 V to 3.6 V | — |
| Internal Frequency (max) | 250 MHz | — |
| Propagation Delay | 0.6 ns | — |
| 패키지 | 240-BQFP (PQFP, 32x32 mm) | 240-BFQFP (240-PQFP / FQFP / QFP-240) |
| 실장 유형 | Surface Mount (gull-wing) | Surface Mount |
| 동작 온도 | 0 C to 70 C (Commercial) | 0 C to +70 C (Commercial) |
| Speed Grade | -1 | — |
| Lead-Free / Pb-Free | Yes (N suffix) | — |
| Configuration Method | Serial / JTAG / EPC | — |
| RoHS 상태 | Compliant (per N suffix Pb-free) | [DATA_NEEDED: RoHS status - legacy Altera FLEX 10K family typically non-RoHS Pb-bearing BFQFP; verify on distributor listing] |
| Family | — | FLEX 10K |
| Typical Gate Count | — | 50,000 gates |
| Logic Elements (LABs) | — | 360 |
| Logic Cells | — | 2,880 |
| Embedded Array Memory | — | 20,480 bits |
| User I/O Pins | — | 189 |
| Number of Terminals | — | 240 |
| Terminal Form | — | Gull Wing |
| Package Code | — | FQFP |
| Package Shape | — | Square |
| Process Technology | — | 0.42 micrometer CMOS, 4-layer metal |
| Core Supply Voltage | — | 3.3 V |
| I/O Supply Voltage (MultiVolt) | — | 5.0 V / 3.3 V / 2.5 V |
| Maximum Internal Frequency | — | 125 MHz |
| Propagation Delay (typical) | — | 0.6 ns |
| Temperature Grade | — | Commercial |
| Configuration Scheme | — | SRAM-based, serial / parallel via EPC1/EPC2 |
| JTAG / Boundary Scan | — | IEEE 1149.1 compliant |