EPM3064ALC44-10 vs EPM3064ATI44-10 비교

다음의 상세 나란히 비교: EPM3064ALC44-10 제조: Altera 및 EPM3064ATI44-10 제조: Intel. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.

사양 비교

파라미터 EPM3064ALC44-10 EPM3064ATI44-10
브랜드 Altera Intel
카테고리 FPGA & CPLD FPGA & CPLD
수명 주기 상태 NRND NRND
재고 상태 In Stock In Stock
단가 (USD) $4.12 $7.65
Family MAX 3000A MAX 3000A
Logic Elements / Macrocells 64 macrocells —
Number of Logic Array Blocks (LABs) 4 4
Usable Gates 1,250 —
Maximum User I/O Pins 34 —
Supply Voltage (VCCINT) 3.3 V 3.3 V
Pin-to-Pin Delay (tPD) 10 ns 10 ns
Maximum Counter Frequency (fCNT) 192.3 MHz —
Maximum Operating Frequency (fMAX) [DATA_NEEDED: fMAX internal] —
패키지 44-PLCC (J-Lead) TQFP-44 (10x10 mm, 0.8 mm pitch)
Process Technology 0.30 µm CMOS EEPROM CMOS, EEPROM
Programmability In-system programmable (JTAG IEEE 1149.1) —
MultiVolt I/O 2.5V / 3.3V / 5.0V interface compatible —
동작 온도 0°C to +70°C (commercial) -40C to +85C (Industrial)
RoHS 상태 Compliant (lead-free L suffix indicates Pb-free package) Non-Compliant (contains lead, per DigiChip listing)
실장 유형 Surface Mount (PLCC socket compatible) Surface Mount
Product Type — CPLD (Complex Programmable Logic Device)
Programmable Type — In-System Programmable (ISP), EEPROM-based
Number of Macrocells — 64
Number of Usable Gates — 1,250
Number of User I/O Pins — 34
Maximum Counter Frequency — 227.3 MHz
I/O Voltage Tolerance — 5.0 V tolerant (MultiVolt I/O)
JTAG Interface — IEEE Std. 1149.1 compliant
ISP Standard — IEEE Std. 1532
Lead Free Status — Contains Lead
Programming Cycles — [DATA_NEEDED: typical program/erase endurance]

데이터시트 & 자료

모든 제품 보기 BOM 생성 견적 요청