EPM3064ATI100-10N vs EPM3064ATC100-10 비교
다음의 상세 나란히 비교: EPM3064ATI100-10N 제조: Altera 및 EPM3064ATC100-10 제조: Altera. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.
Altera
EPM3064ATC100-10 - 64-Macrocell MAX 3000A CPLD, 100MHz, TQFP-100 | Altera
EPM3064ATC100-10 Nrnd사양 비교
| 파라미터 | EPM3064ATI100-10N | EPM3064ATC100-10 |
|---|---|---|
| 브랜드 | Altera | Altera |
| 카테고리 | FPGA & CPLD | FPGA & CPLD |
| 수명 주기 상태 | 활성 | NRND |
| 재고 상태 | In Stock | In Stock |
| 단가 (USD) | $9.80 | $2.85 |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Programmable Type | In-System Programmable (ISP) via IEEE 1149.1 JTAG | — |
| Technology | CMOS EEPROM | — |
| Usable Gates | 1,250 | — |
| Macrocells | 64 | 64 |
| Logic Array Blocks (LABs) | 4 | — |
| User I/O | 66 | — |
| Supply Voltage (Core / I/O) | 3.3 V | — |
| Pin-to-Pin Delay (tPD) | 10 ns (-10 speed grade) | — |
| Maximum Internal Frequency | 227.3 MHz (counter) | — |
| 패키지 | 100-pin TQFP (industrial) | TQFP-100 (100-pin Thin Quad Flat Pack) |
| 동작 온도 | -40 C to +85 C (industrial) | — |
| JTAG (IEEE 1149.1) | Yes | — |
| PCI Compliance | PCI Local Bus Specification Revision 2.2 (-4/-5/-6/-7/-10 speed grades) | — |
| MultiVolt I/O | Supports 2.5 V / 3.3 V / 5 V mixed-voltage interfacing | — |
| Lead-Free Status | Contains Lead | — |
| RoHS 상태 | RoHS Non-Compliant | [DATA_NEEDED: RoHS compliance] |
| Logic Gates | — | 1250 gates |
| Logic Array Blocks | — | 2 |
| User I/O Pins | — | 34 |
| Propagation Delay (tPD) | — | 10 ns |
| Supply Voltage (VCCINT) | — | 3.3 V |
| Process Technology | — | CMOS EEPROM |
| In-System Programmability | — | IEEE Std. 1149.1 (JTAG) and IEEE Std. 1532 compliant |
| Global Clock Signals | — | 2 (with optional inversion) |
| Output Enable Signals | — | 6 or 10 pin- or logic-driven |
| Output Slew-Rate Control | — | Programmable |
| Operating Temperature Grade | — | Commercial |
| MultiVolt I/O Support | — | 1.5V / 1.8V / 2.5V / 3.3V interfaces |