EPM3256AFC256-7 vs EPM3256AFC256-10 비교
다음의 상세 나란히 비교: EPM3256AFC256-7 제조: Altera 및 EPM3256AFC256-10 제조: Altera. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.
Altera
EPM3256AFC256-10 - 256-Macro CPLD MAX 3000A | Intel / Altera | FBGA-256
EPM3256AFC256-10 ⚠ 최종 구매사양 비교
| 파라미터 | EPM3256AFC256-7 | EPM3256AFC256-10 |
|---|---|---|
| 브랜드 | Altera | Altera |
| 카테고리 | FPGA & CPLD | FPGA & CPLD |
| 수명 주기 상태 | Obsolete | 최종 구매 |
| 재고 상태 | In Stock | In Stock |
| 단가 (USD) | $12.10 | $19.95 |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Macro Cells | 256 | 256 |
| Logic Array Blocks (LABs) | 16 | 16 (16 macrocells each) |
| Usable Gates | 10,000 | 5,000 |
| User I/Os | 161 | — |
| Pin-to-Pin Logic Delay | 4.5 ns (max) | — |
| Counter Frequency | 227.3 MHz (max) | — |
| Propagation Delay (tpd) | 10 ns | — |
| Core Voltage | 3.3 V | — |
| I/O Compatibility | 5.0 V / 3.3 V / 2.5 V (MultiVolt I/O) | — |
| Process Technology | CMOS EEPROM, 0.30 µm | — |
| In-System Programmability | IEEE Std. 1532-compliant 3.3-V ISP | Yes (3.3 V ISP via JTAG IEEE 1149.1) |
| Boundary-Scan Test | JTAG (IEEE 1149.1) | — |
| 패키지 | FBGA-256 (FineLine BGA), 256 balls | 256-ball FBGA (Fine-Line BGA) |
| 동작 온도 | 0 °C to 70 °C (Commercial) | 0°C to +70°C (Commercial) |
| Speed Grade | -7 | — |
| RoHS 상태 | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: RoHS compliance status] |
| Logic Family | — | CMOS (EEPROM-based) |
| Maximum User I/Os | — | 161 |
| Propagation Delay (tPD) | — | 10 ns |
| Internal Counter Frequency (fCNT) | — | 95.2 MHz |
| Supply Voltage (VCCINT) | — | 3.3 V |
| I/O Voltage Tolerance | — | 5.0 V tolerant |
| Pitch | — | [DATA_NEEDED: BGA ball pitch] |
| 실장 유형 | — | Surface Mount |