EPM3512AFI256-10N vs EPM3512AFI256-7N 비교

다음의 상세 나란히 비교: EPM3512AFI256-10N 제조: Altera 및 EPM3512AFI256-7N 제조: Altera. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.

Altera
EPM3512AFI256-7N EPM3512AFI256-7N - MAX 3000A CPLD, 512 Macrocells | Intel / Altera

EPM3512AFI256-7N - MAX 3000A CPLD, 512 Macrocells | Intel / Altera

EPM3512AFI256-7N ⚠ 최종 구매

사양 비교

파라미터 EPM3512AFI256-10N EPM3512AFI256-7N
브랜드 Altera Altera
카테고리 FPGA & CPLD FPGA & CPLD
수명 주기 상태 최종 구매 최종 구매
재고 상태 In Stock In Stock
단가 (USD) $21.75 $27.95
Family MAX 3000A MAX 3000A
Series EPM3512 —
Device Type CPLD (Complex Programmable Logic Device) —
Architecture CMOS EEPROM-based, MAX architecture —
Number of Macrocells 512 —
Number of Logic Array Blocks (LABs) 16 —
Usable Gates Up to 10,000 —
Number of User I/O 208 —
Total Pins 256 —
Pin-to-Pin Propagation Delay (tPD) 10 ns —
Maximum Counter Frequency 227.3 MHz —
Core Supply Voltage (VCCINT) 3.3 V (3.0 V to 3.6 V) —
I/O Supply Voltage (VCCIO) 2.5 V or 3.3 V (5.0 V tolerant inputs) —
MultiVolt I/O Support 5.0 V / 3.3 V / 2.5 V —
In-System Programmability Yes - IEEE Std 1532 compliant —
JTAG Boundary Scan Yes - IEEE 1149.1 —
Program Memory EEPROM (non-volatile) —
패키지 256-ball FineLine BGA (FBGA-256) 256-ball FBGA
실장 유형 Surface Mount Surface Mount (BGA)
동작 온도 범위 -40 °C to +85 °C (industrial) -40C to +85C (industrial)
RoHS 상태 Compliant —
Speed Grade -10 (10 ns tPD) -7
Device Logic Elements / Macrocells — 512 macrocells
Typical Usable Gates — 10,000 gates
Logic Array Blocks (LABs) — 16
Maximum User I/O Pins — [DATA_NEEDED: user I/O count]
Maximum Operating Frequency (fMAX) — 116.3 MHz
Pin-to-Pin Delay (tPD, speed grade -7) — approximately 7.5 ns
Supply Voltage (VCCINT) — 3.3 V
MultiVolt I/O Levels — 2.5 V / 3.3 V / 5 V mixed
Configuration Memory — Non-volatile EEPROM
Programming Interface — IEEE 1149.1 JTAG (in-system programmable)
Lead-Free / RoHS — Yes ('N' suffix, lead-free)
Design Software — Quartus II (legacy MAX 3000A support)

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