EPM3512AQC208-10S vs EPM3512AQC20-10 비교
다음의 상세 나란히 비교: EPM3512AQC208-10S 제조: Altera 및 EPM3512AQC20-10 제조: Altera. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.
사양 비교
| 파라미터 | EPM3512AQC208-10S | EPM3512AQC20-10 |
|---|---|---|
| 브랜드 | Altera | Altera |
| 카테고리 | FPGA & CPLD | FPGA & CPLD |
| 수명 주기 상태 | Obsolete | NRND |
| 재고 상태 | In Stock | In Stock |
| 단가 (USD) | $9.75 | $21.10 |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Macrocells | 512 | 512 |
| Usable Gates | 1750 | — |
| Logic Array Blocks (LABs) | 32 (16 macrocells each) | 16 |
| 패키지 | 208-pin FineLine BGA-256 | PQFP-240 (QC20 designation per Altera ordering code) |
| User I/Os | 208 | — |
| Speed Grade | -10 (tPD1 = 7.5 ns) | — |
| Propagation Delay (tPD1) | 7.5 ns (pin-to-pin) | — |
| Supply Voltage - VCCINT (internal) | 3.3 V | — |
| Supply Voltage - VCCIO (I/O) | 2.5 V, 3.3 V, or 5.0 V (MultiVolt) | — |
| Programming Technology | CMOS EEPROM | — |
| In-System Programmability (ISP) | Yes (IEEE Std. 1149.1 JTAG) | — |
| PCI Compliance | Yes (PCI Local Bus Specification Rev 2.2) | — |
| 동작 온도 | 0C to +70C (commercial) | 0C to +70C (commercial) |
| Boundary-Scan (JTAG) | Yes (1149.1 compliant) | — |
| Program/Erase Endurance | 100 cycles minimum | — |
| Logic Family | CMOS | — |
| Process Technology | EEPROM-based CMOS | 0.30 µm EEPROM CMOS |
| RoHS 상태 | [DATA_NEEDED: rohs_status] | Compliant (lead-free PQFP package) |
| Macrocells per LAB | — | 32 |
| User I/O Pins | — | 100 |
| Pin-to-Pin Delay (tPD) | — | 10 ns |
| Maximum Frequency (fCNT) | — | 116.3 MHz |
| Supply Voltage VCCINT | — | 5.0 V |
| MultiVolt I/O Voltages | — | 5.0 V / 3.3 V / 2.5 V / 1.8 V |
| Programming Interface | — | IEEE 1149.1 (JTAG) - In-System Programmable |