EPM5016DC-15 vs EPM5016PC-1 비교
다음의 상세 나란히 비교: EPM5016DC-15 제조: Altera 및 EPM5016PC-1 제조: Altera. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.
사양 비교
| 파라미터 | EPM5016DC-15 | EPM5016PC-1 |
|---|---|---|
| 브랜드 | Altera | Altera |
| 카테고리 | FPGA & CPLD | FPGA & CPLD |
| 수명 주기 상태 | Obsolete | Obsolete |
| 재고 상태 | In Stock | In Stock |
| 단가 (USD) | $10.75 | $9.95 |
| Device Family | MAX 5000 | — |
| Product Type | EPLD (Erasable Programmable Logic Device) | — |
| Macrocells | 16 | 16 |
| Logic Array Blocks (LABs) | 2 | 1 |
| Dedicated Inputs | 4 | — |
| User I/O Pins | 12 | — |
| Pin-to-Pin Delay (tpd) | 15 ns | — |
| Maximum Frequency (fmax) | 71 MHz | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | 4.75 V to 5.25 V |
| Programming Voltage (VPP) | 12.75 V | — |
| 동작 온도 | 0 °C to 70 °C (commercial) | 0 C to +70 C (commercial) |
| 패키지 | Ceramic DIP-24 (windowed) | PDIP-20 (plastic DIP, through-hole) |
| 실장 유형 | Through-Hole | — |
| Process Technology | CMOS EPROM | — |
| Configuration Memory | Non-volatile UV-erasable EPROM | CMOS EEPROM (UV-erasable) |
| RoHS 상태 | [DATA_NEEDED: RoHS status - pre-RoHS era part, likely non-compliant] | Non-compliant (PDIP with SnPb leads, pre-RoHS era) |
| Lead Finish | [DATA_NEEDED: lead-free status] | — |
| Family | — | MAX 5000 EPLD |
| Usable Gates | — | 200 |
| Propagation Delay (tPD) | — | 35 ns |
| Maximum Frequency (fMAX) | — | 62 MHz |
| Setup Time (tSU) | — | [DATA_NEEDED: setup time ns] |
| Supply Current (ICC) | — | 50 mA typical |
| 핀 수 | — | 20 |
| Programming Interface | — | Altera 4-pin JTAG-style (MasterBlaster / ByteBlaster) |