EPM5032DC-20 vs EPM5032DI-20 비교

다음의 상세 나란히 비교: EPM5032DC-20 제조: Intel 및 EPM5032DI-20 제조: Intel. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.

사양 비교

파라미터 EPM5032DC-20 EPM5032DI-20
브랜드 Intel Intel
카테고리 FPGA & CPLD FPGA & CPLD
수명 주기 상태 Obsolete Obsolete
재고 상태 In Stock In Stock
단가 (USD) $5.05 $8.75
Product Family MAX 5000 —
Device Type CPLD (Complex Programmable Logic Device) —
Programmable Technology UV-Erasable / OTP EPROM —
Usable Gates 600 —
Macrocells 32 32
Maximum Frequency (fCNT) 71.4 MHz —
Pin-to-Pin Delay (tPD) 20 ns —
Speed Grade -20 —
Supply Voltage (VCC) 5 V —
패키지 20-pin DIP (Windowed Ceramic, 0.3" wide) Ceramic DIP-20 (windowed, UV-erasable)
실장 유형 Through-Hole —
Logic Blocks 4 Logic Array Blocks (LABs) —
I/O Pins [DATA_NEEDED: I/O pin count for DIP-20 variant] —
동작 온도 [DATA_NEEDED: commercial/industrial/military grade] Industrial (per 'I' suffix)
RoHS 상태 Compliant (per IC-Components listing) [DATA_NEEDED: RoHS compliance status for ceramic DIP variant]
Lead Free [DATA_NEEDED: confirmed lead-free] —
Manufacturer Altera (now Intel Programmable Solutions Group) —
Programming Method Altera MAX+PLUS II / Quartus (legacy support) —
Family — MAX 5000 (Altera legacy EPLD)
Architecture — CMOS PAL-type EPLD with PIA
Dedicated Inputs — 7
Bidirectional I/O Pins — 16
Product Terms — 320 (maximum)
Flip-Flops — 16 (one per macrocell)
최대 클록 주파수 — 62.5 MHz
Pin-to-Pin Delay — 20 ns (speed grade -20)
Programming — UV-erasable CMOS, JEDEC fuse file
Development Tool — Altera MAX+PLUS II (legacy)
Lead-Free — [DATA_NEEDED: lead-free status]

데이터시트 & 자료

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