EPM5032JC vs EPM5064JC-1 비교
다음의 상세 나란히 비교: EPM5032JC 제조: Altera 및 EPM5064JC-1 제조: Altera. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.
사양 비교
| 파라미터 | EPM5032JC | EPM5064JC-1 |
|---|---|---|
| 브랜드 | Altera | Altera |
| 카테고리 | FPGA & CPLD | FPGA & CPLD |
| 수명 주기 상태 | Obsolete | NRND |
| 재고 상태 | In Stock | In Stock |
| 단가 (USD) | $13.50 | $18.25 |
| Family | MAX 5000 EPLD | MAX 5000 |
| Macrocells | 32 | — |
| Logic Gates | 600 usable gates | — |
| Maximum I/O Pins | 40 | — |
| Propagation Delay (tPD) | [DATA_NEEDED: specific speed grade value] | — |
| Supply Voltage (VCC) | 5 V | 5 V nominal (4.75 V – 5.25 V) |
| Input Type | TTL-compatible | — |
| 출력 유형 | TTL/CMOS-compatible | — |
| 패키지 | PLCC-44 | 44-pin PLCC (J-lead, windowed ceramic) |
| 동작 온도 | 0C to +70C (commercial) | 0 °C to +70 °C (commercial, -JC suffix) |
| 실장 유형 | Surface Mount (J-lead) | Surface Mount (PLCC socket recommended) |
| Programmability | UV-erasable (windowed ceramic) / OTP variants | — |
| Design Software | MAX+PLUS II / Quartus legacy | — |
| JEDEC Standard | JEDEC PLCC-44 footprint | — |
| RoHS 상태 | unknown | Non-compliant (windowed ceramic, contains Pb in glass frit) |
| Lead-Free | unknown | — |
| Device Type | — | EPLD (Erasable Programmable Logic Device) |
| Macro Cells | — | 64 |
| Usable Gates | — | 1250 (typical) |
| Logic Elements | — | 128 (Logic Array Blocks) |
| Maximum Operating Frequency | — | 33.3 MHz (fCNT) |
| Pin-to-Pin Delay (tPD) | — | [DATA_NEEDED: tPD typical/max in ns] |
| Process Technology | — | 0.8 µm CMOS |
| Programmable Pins | — | 36 (typical I/O, 44-pin PLCC) |
| Dedicated Inputs | — | [DATA_NEEDED: dedicated input count] |
| Erasure Method | — | UV-erasable through quartz window |
| Programming Method | — | Altera Logic Programmer + MasterBlaster/ByteBlasterMV |
| JTAG Boundary Scan | — | Not supported (classic MAX architecture) |
| Military/Avionics SMD | — | 5962-01-417-3750 (QML variant: EPM5064JM/883) |