EPM5128GC-1 vs EPM5064JC-1 비교

다음의 상세 나란히 비교: EPM5128GC-1 제조: Altera 및 EPM5064JC-1 제조: Altera. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.

사양 비교

파라미터 EPM5128GC-1 EPM5064JC-1
브랜드 Altera Altera
카테고리 FPGA & CPLD FPGA & CPLD
수명 주기 상태 Obsolete NRND
재고 상태 In Stock In Stock
단가 (USD) $18.95 $18.25
Family MAX 5000 MAX 5000
Device Type UV-erasable CMOS CPLD EPLD (Erasable Programmable Logic Device)
Macrocells 128 —
Usable Gates 2,500 1250 (typical)
Dedicated Inputs 7 [DATA_NEEDED: dedicated input count]
Maximum User I/O Pins 52 —
Nominal Supply Voltage 5 V —
Supply Voltage Range 4.75 V to 5.25 V —
Maximum Operating Frequency 62.5 MHz 33.3 MHz (fCNT)
Propagation Delay (tPD) 16 ns (typical, -1 speed grade) —
패키지 PGA-96+ (Pin Grid Array, ceramic windowed) 44-pin PLCC (J-lead, windowed ceramic)
Technology CMOS, UV-erasable EPROM —
동작 온도 -40C to +85C (industrial) 0 °C to +70 °C (commercial, -JC suffix)
IOL / IOH 100 mA / 25 mA per pin (legacy figure, [DATA_NEEDED: verify exact drive spec]) —
Security Bit Programmable, prevents readback —
Programming Method UV erase + EPROM program (or device programmer) Altera Logic Programmer + MasterBlaster/ByteBlasterMV
MSL 레벨 [DATA_NEEDED: MSL level] —
RoHS 상태 [DATA_NEEDED: RoHS compliance - ceramic PGA part is legacy] Non-compliant (windowed ceramic, contains Pb in glass frit)
Macro Cells — 64
Logic Elements — 128 (Logic Array Blocks)
Pin-to-Pin Delay (tPD) — [DATA_NEEDED: tPD typical/max in ns]
Supply Voltage (VCC) — 5 V nominal (4.75 V – 5.25 V)
Process Technology — 0.8 µm CMOS
Programmable Pins — 36 (typical I/O, 44-pin PLCC)
실장 유형 — Surface Mount (PLCC socket recommended)
Erasure Method — UV-erasable through quartz window
JTAG Boundary Scan — Not supported (classic MAX architecture)
Military/Avionics SMD — 5962-01-417-3750 (QML variant: EPM5064JM/883)

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