EPM5192AJC84-15 vs EPM5192AGC84-20 비교
다음의 상세 나란히 비교: EPM5192AJC84-15 제조: Altera 및 EPM5192AGC84-20 제조: Altera. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.
Altera
EPM5192AJC84-15 - MAX 5000 CPLD, 192 Macrocells, 84-pin PLCC | Altera
EPM5192AJC84-15 Obsolete
사양 비교
| 파라미터 | EPM5192AJC84-15 | EPM5192AGC84-20 |
|---|---|---|
| 브랜드 | Altera | Altera |
| 카테고리 | FPGA & CPLD | FPGA & CPLD |
| 수명 주기 상태 | Obsolete | Obsolete |
| 재고 상태 | In Stock | In Stock |
| 단가 (USD) | $18.95 | $41.20 |
| Family | MAX 5000 | MAX 5000 |
| Device Type | EPLD (Erasable Programmable Logic Device) | — |
| Macrocells | 192 | 192 |
| Propagation Delay (tpd) | 15 ns | — |
| Maximum Clock Frequency (fMAX) | 83.3 MHz | 66.7 MHz |
| Supply Voltage (VCC) | 5 V (single supply) | — |
| Technology | CMOS, UV-erasable EPROM | — |
| 패키지 | 84-pin PLCC (J84C) windowed ceramic | 84-pin Ceramic Pin Grid Array (CPGA, WPGA) |
| 실장 유형 | Surface Mount | Through-Hole (Pin Grid Array socket) |
| 동작 온도 | [DATA_NEEDED: commercial/industrial/military grade] | — |
| Programming Method | UV-erase + EPROM programming (windowed package) | — |
| Logic Blocks | 16 Logic Array Blocks (LABs) | — |
| I/O Pins | [DATA_NEEDED: user I/O count] | — |
| RoHS 상태 | Non-compliant (contains Pb, ceramic windowed package) | [DATA_NEEDED: RoHS compliance] |
| Process Technology | CMOS EPROM | CMOS |
| Product Type | — | Complex Programmable Logic Device (CPLD) |
| User I/O Pins | — | 64 |
| Dedicated Inputs | — | 7 |
| Logic Gates (typical) | — | [DATA_NEEDED: typical gate count] |
| Pin-to-Pin Delay (tPD) | — | 20 ns |
| Speed Grade | — | -20 |
| Package Code | — | WPGA |
| Erasure Method | — | UV-Erasable (with OTP window) |
| Operating Temperature Grade | — | Commercial |
| 공급 전압 | — | [DATA_NEEDED: VCC range] |
| I/O Standard | — | 5V CMOS / TTL compatible |