EPM5192GI84 vs EPM5192GC84-1 비교

다음의 상세 나란히 비교: EPM5192GI84 제조: Altera 및 EPM5192GC84-1 제조: Altera. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.

사양 비교

파라미터 EPM5192GI84 EPM5192GC84-1
브랜드 Altera Altera
카테고리 FPGA & CPLD FPGA & CPLD
수명 주기 상태 Obsolete Obsolete
재고 상태 In Stock In Stock
단가 (USD) $19.80 $14.20
Family MAX 5000 MAX 5000
Device Type UV-Erasable / OTP Complex PLD (CPLD) —
Macrocells 192 192
Logic Array Blocks [DATA_NEEDED: number of LABs] —
패키지 84-pin PGA (WPGA, square, through-hole, pin/peg terminals) 84-pin PGA (Pin Grid Array), WPGA code
Package Code WPGA —
Operating Voltage (VCC) 5 V (typical) —
I/O Logic Compatibility TTL —
Temperature Grade Industrial Commercial
Programmable Flip-Flop Modes D, T, JK, SR —
Programmability UV-erasable (windowed) / OTP —
Programming File Format JEDEC map via MAX+PLUS II / A+PLUS —
Propagation Delay [DATA_NEEDED: tPD in ns] —
Max User I/O Pins [DATA_NEEDED: usable I/O count for this package] —
동작 온도 범위 -40 C to +85 C (industrial) —
실장 유형 Through-Hole (PGA socket or PCB pin/peg) Through-hole (PGA socket)
RoHS 상태 [DATA_NEEDED: most legacy PGA parts are non-RoHS] Compliant (per third-party distributor listing)
Lead-Free [DATA_NEEDED: legacy part, likely contains lead] —
Number of Terminals 84 —
Terminal Form PIN/PEG —
Package Shape SQUARE —
Product Type — UV-Erasable/OTP Complex PLD (CPLD)
Technology — CMOS (EPROM-cell based)
Propagation Delay (tPD) — 40 ns (speed grade -1)
최대 클록 주파수 — 50 MHz
Supply Voltage (VCC) — 4.75 V to 5.25 V
Dedicated Inputs — 7
User I/O Pins — 64
Total Inputs / Outputs — 72 inputs / 64 outputs
Architecture — Shared input/clock and shared product terms
Programming Method — UV erasure (quartz window) + EPROM programmer
Logic Element Type — Macrocells with AND/OR array

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