EPM5192GI84 vs EPM5192LI84 비교

다음의 상세 나란히 비교: EPM5192GI84 제조: Altera 및 EPM5192LI84 제조: Altera. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.

사양 비교

파라미터 EPM5192GI84 EPM5192LI84
브랜드 Altera Altera
카테고리 FPGA & CPLD FPGA & CPLD
수명 주기 상태 Obsolete Obsolete
재고 상태 In Stock In Stock
단가 (USD) $19.80 $21.60
Family MAX 5000 —
Device Type UV-Erasable / OTP Complex PLD (CPLD) —
Macrocells 192 —
Logic Array Blocks [DATA_NEEDED: number of LABs] —
패키지 84-pin PGA (WPGA, square, through-hole, pin/peg terminals) —
Package Code WPGA —
Operating Voltage (VCC) 5 V (typical) —
I/O Logic Compatibility TTL —
Temperature Grade Industrial —
Programmable Flip-Flop Modes D, T, JK, SR —
Programmability UV-erasable (windowed) / OTP —
Programming File Format JEDEC map via MAX+PLUS II / A+PLUS —
Propagation Delay [DATA_NEEDED: tPD in ns] —
Max User I/O Pins [DATA_NEEDED: usable I/O count for this package] —
동작 온도 범위 -40 C to +85 C (industrial) -40 °C to +85 °C (industrial)
실장 유형 Through-Hole (PGA socket or PCB pin/peg) Surface Mount (socket-compatible)
RoHS 상태 [DATA_NEEDED: most legacy PGA parts are non-RoHS] [DATA_NEEDED: RoHS compliance status]
Lead-Free [DATA_NEEDED: legacy part, likely contains lead] —
Number of Terminals 84 —
Terminal Form PIN/PEG —
Package Shape SQUARE —
Device Family — MAX 5000
Product Type — UV-Erasable/OTP Complex PLD (CPLD)
Usable Gates — 3,750 gates
Macro Cells — 192
Maximum Toggle Frequency — 40 MHz
Pin-to-Pin Delay (tPD) — 25 ns
Supply Voltage (VCC) — 5 V (single supply)
User I/O Pins — 64 (max)
Package Type — 84-pin PLCC (J-lead, package code J84/QCCJ)
Configuration Memory — OTP / UV-erasable EPROM
Programming Method — Stand-alone programmer (no JTAG on LI84 OTP variant)
Logic Compatibility — TTL-compatible I/O

데이터시트 & 자료

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