EPM5192JI vs EPM5192JI-2 비교
다음의 상세 나란히 비교: EPM5192JI 제조: Altera 및 EPM5192JI-2 제조: Altera. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.
사양 비교
| 파라미터 | EPM5192JI | EPM5192JI-2 |
|---|---|---|
| 브랜드 | Altera | Altera |
| 카테고리 | FPGA & CPLD | FPGA & CPLD |
| 수명 주기 상태 | Obsolete | Obsolete |
| 재고 상태 | In Stock | In Stock |
| 단가 (USD) | $9.75 | $9.95 |
| Family | MAX 5000 | MAX 5000 |
| Device Type | EPLD (UV-erasable CMOS Programmable Logic Device) | EPLD (Erasable Programmable Logic Device) |
| Macrocells | 192 | 192 |
| Logic Array Blocks (LABs) | 12 | — |
| User I/O Pins | 64 | — |
| Dedicated Inputs | 7 | 12 |
| Propagation Delay (tpd) | 55 ns | — |
| 공급 전압 | 4.75 V to 5.25 V (nominal 5 V) | 5 V (typical) |
| Technology | CMOS EPROM, UV-erasable | — |
| 패키지 | 84-pin PLCC (windowed, J-suffix ceramic) | JLCC-68 (J-Lead Ceramic) |
| 동작 온도 | -40 C to +125 C (industrial, I-suffix) | 0C to +70C (commercial) |
| 실장 유형 | Surface Mount (PLCC socket recommended for UV erasure) | Surface Mount |
| RoHS 상태 | [DATA_NEEDED: RoHS status - pre-2010 part, likely non-compliant] | Non-compliant (ceramic JLCC, contains lead) |
| Programming Method | Altera MAX 5000 programming algorithm (device programmer) | — |
| Erasure Method | UV exposure through windowed package | — |
| Usable Gates | — | 5000 |
| Flip-Flops | — | 192 |
| Speed Grade | — | -2 |
| Programming Technology | — | UV-Erasable EPROM |
| Architecture | — | Sum-of-products with Programmable Interconnect Array (PIA) |
| Process Technology | — | CMOS EPROM |
| 수명 주기 상태 | — | Obsolete (legacy Altera MAX 5000 family) |