EPM5192LC vs EPM5192LC-2N 비교
다음의 상세 나란히 비교: EPM5192LC 제조: Altera 및 EPM5192LC-2N 제조: Altera. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.
사양 비교
| 파라미터 | EPM5192LC | EPM5192LC-2N |
|---|---|---|
| 브랜드 | Altera | Altera |
| 카테고리 | FPGA & CPLD | FPGA & CPLD |
| 수명 주기 상태 | Obsolete | Obsolete |
| 재고 상태 | In Stock | In Stock |
| 단가 (USD) | $28.40 | $11.85 |
| Family | MAX 7000S | MAX 5000 |
| Macrocells | 192 | 192 |
| Logic Array Blocks (LABs) | 12 | — |
| User I/O Pins | 64 | — |
| Dedicated Inputs | 7 | — |
| Global Clock Inputs | 1 | — |
| Propagation Delay (tPD) | 55 ns (typical, commercial) | — |
| Maximum Clock Frequency (fMAX) | 50 MHz | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (nominal 5 V) | — |
| Process Technology | CMOS, UV-erasable/OTP EPROM configuration | — |
| Programmable Interconnect | Programmable Interconnect Array (PIA), fixed delay | — |
| Boundary-Scan Support | JTAG IEEE 1149.1 | — |
| Programming Interface | JTAG (ByteBlaster-compatible) | Altera programming hardware (MAX+PLUS II / ByteBlaster compatible) |
| Operating Temperature (commercial) | 0C to +70C | — |
| 패키지 | JLCC-68 (windowed ceramic, LC suffix) | — |
| 실장 유형 | Surface Mount | Surface Mount (LC package) |
| RoHS 상태 | [DATA_NEEDED: RoHS status] | Compliant (per -N lead-free suffix) |
| Flip-Flops | — | 192 |
| Logic Elements | — | 192 macrocells (PAL/GAL-style AND-OR array) |
| Package Type | — | LC (ceramic J-leaded, windowed UV-erasable package family) |
| Speed Grade | — | -2 (tPD approximately 25 ns) |
| Propagation Delay (typical) | — | 25 ns |
| 공급 전압 | — | 5 V (typical) |
| Programmability | — | UV-erasable EPROM cell |
| 동작 온도 | — | Commercial (0C to +70C) - inferred from speed-grade -2 designation |
| Lead-Free | — | Yes (per -N suffix) |
| Architecture | — | Programmable Logic Array (PLA) with global PIA |