EPM5192LC84 vs EPM5192GI84 비교
다음의 상세 나란히 비교: EPM5192LC84 제조: Altera 및 EPM5192GI84 제조: Altera. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.
사양 비교
| 파라미터 | EPM5192LC84 | EPM5192GI84 |
|---|---|---|
| 브랜드 | Altera | Altera |
| 카테고리 | FPGA & CPLD | FPGA & CPLD |
| 수명 주기 상태 | Obsolete | Obsolete |
| 재고 상태 | In Stock | In Stock |
| 단가 (USD) | $15.95 | $19.80 |
| Product Type | Complex Programmable Logic Device (CPLD) | — |
| Family | MAX 5000 | MAX 5000 |
| Macrocells (Logic Cells) | 192 | — |
| Propagation Delay (tPD) | 55 ns | — |
| Process Technology | CMOS | — |
| Programmability | OTP / UV-Erasable | UV-erasable (windowed) / OTP |
| 패키지 | LCC-84 (PQCC84, MS-018) | 84-pin PGA (WPGA, square, through-hole, pin/peg terminals) |
| 핀 수 | 84 | — |
| 실장 유형 | Surface Mount (Socket-compatible) | Through-Hole (PGA socket or PCB pin/peg) |
| 동작 온도 | [DATA_NEEDED: operating temperature range] | — |
| 공급 전압 | [DATA_NEEDED: VCC range] | — |
| User I/O | [DATA_NEEDED: max user I/O count] | — |
| Configuration Memory | EPROM / UV-Erasable | — |
| Programming Interface | JTAG / Altera legacy (MAX+PLUS II baseline) | — |
| RoHS 상태 | unknown | [DATA_NEEDED: most legacy PGA parts are non-RoHS] |
| MSL 레벨 | [DATA_NEEDED: MSL rating] | — |
| Device Type | — | UV-Erasable / OTP Complex PLD (CPLD) |
| Macrocells | — | 192 |
| Logic Array Blocks | — | [DATA_NEEDED: number of LABs] |
| Package Code | — | WPGA |
| Operating Voltage (VCC) | — | 5 V (typical) |
| I/O Logic Compatibility | — | TTL |
| Temperature Grade | — | Industrial |
| Programmable Flip-Flop Modes | — | D, T, JK, SR |
| Programming File Format | — | JEDEC map via MAX+PLUS II / A+PLUS |
| Propagation Delay | — | [DATA_NEEDED: tPD in ns] |
| Max User I/O Pins | — | [DATA_NEEDED: usable I/O count for this package] |
| 동작 온도 범위 | — | -40 C to +85 C (industrial) |
| Lead-Free | — | [DATA_NEEDED: legacy part, likely contains lead] |
| Number of Terminals | — | 84 |
| Terminal Form | — | PIN/PEG |
| Package Shape | — | SQUARE |