EPM7128AETI100-7 vs EPM7128AETI100-7N 비교
다음의 상세 나란히 비교: EPM7128AETI100-7 제조: Altera 및 EPM7128AETI100-7N 제조: Altera. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.
Altera
EPM7128AETI100-7 - MAX 7000A CPLD, 128 Macrocells, 100-TQFP | Altera
EPM7128AETI100-7 ObsoleteAltera
EPM7128AETI100-7N - MAX 7000A CPLD 128 Macro 84 I/O | Intel/Altera
EPM7128AETI100-7N Obsolete사양 비교
| 파라미터 | EPM7128AETI100-7 | EPM7128AETI100-7N |
|---|---|---|
| 브랜드 | Altera | Altera |
| 카테고리 | FPGA & CPLD | FPGA & CPLD |
| 수명 주기 상태 | Obsolete | Obsolete |
| 재고 상태 | In Stock | In Stock |
| 단가 (USD) | $30.10 | $28.50 |
| Family | MAX 7000A | MAX 7000A CPLD |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Macrocells | 128 | — |
| Usable Gates | 2,500 | — |
| User I/Os | 84 | — |
| Logic Blocks (LABs) | 8 | — |
| Pin-to-Pin Delay (tPD) | 7.5 ns | — |
| Maximum Counter Frequency | 129.9 MHz | — |
| Supply Voltage - Core (VCCINT) | 3.3 V | — |
| I/O Bank Supply (VCCIO) | 2.5 V / 3.3 V / 5 V (MultiVolt) | — |
| Configuration Memory | EEPROM (non-volatile, in-system programmable) | — |
| JTAG Support | Yes (IEEE 1149.1 boundary-scan) | — |
| Global Clock Inputs | 4 dedicated | — |
| 패키지 | 100-pin TQFP (1.0 mm pitch, 14 x 14 mm) | 100-pin TQFP (14x14 mm) |
| 동작 온도 | -40 C to +85 C (Industrial) | -40C to +85C (Industrial) |
| 실장 유형 | Surface Mount | Surface Mount |
| RoHS 상태 | [DATA_NEEDED: confirm RoHS for non-N suffix] | Compliant |
| Lead-Free Version (MPN Suffix) | -N suffix denotes lead-free (e.g., EPM7128AETI100-7N) | — |
| Series | — | MAX 7000A |
| Macro Cells | — | 128 |
| Number of Usable Gates | — | 2,500 |
| Number of I/O | — | 84 |
| Number of Logic Array Blocks (LABs) | — | 8 |
| Propagation Delay (tPD max) | — | 7 ns |
| Maximum Operating Frequency (fCNT) | — | 129.9 MHz |
| Supply Voltage (VCCINT) | — | 3.0 V to 3.6 V |
| I/O Bank Voltage (VCCIO) | — | 2.5 V / 3.3 V / 5.0 V (multi-volt I/O) |
| Process Technology | — | CMOS EEPROM |
| In-System Programmability | — | Yes (JTAG IEEE 1149.1) |