EPM7128STC100-15N vs EPM7128STC100-10N 비교
다음의 상세 나란히 비교: EPM7128STC100-15N 제조: Intel 및 EPM7128STC100-10N 제조: Altera. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.
Intel
EPM7128STC100-15N - 128-Macro Cell CPLD, 15ns, 100-TQFP | Intel / Altera
EPM7128STC100-15N ObsoleteAltera
EPM7128STC100-10N - MAX 7000S CPLD 128-Macrocell 10ns TQFP-100 | Altera
EPM7128STC100-10N Nrnd사양 비교
| 파라미터 | EPM7128STC100-15N | EPM7128STC100-10N |
|---|---|---|
| 브랜드 | Intel | Altera |
| 카테고리 | FPGA & CPLD | FPGA & CPLD |
| 수명 주기 상태 | Obsolete | NRND |
| 재고 상태 | In Stock | In Stock |
| 단가 (USD) | $9.20 | $9.30 |
| Product Type | CPLD (Complex Programmable Logic Device) | CPLD - Complex Programmable Logic Device |
| Family | MAX 7000S | MAX 7000S |
| Usable Gates | 2,500 | 2,500 |
| Macro Cells | 128 | — |
| Logic Array Blocks (LABs) | 8 (16 macro cells each) | 8 (16 macrocells each) |
| Maximum User I/O | 84 | — |
| Pin-to-Pin Logic Delay (tPD) | 15 ns (-15 speed grade) | — |
| Maximum Internal Frequency | 76.9 MHz | — |
| Supply Voltage (VCC) | 5 V (4.75 V to 5.25 V) | — |
| Supply Voltage (VCCIO) | 3.3 V or 5 V (per bank) | — |
| Technology | CMOS EEPROM, in-system programmable | — |
| 패키지 | 100-pin TQFP | 100-pin TQFP (14 x 14 x 1 mm) |
| 동작 온도 | 0C to +70C (commercial) | 0 C to +70 C (commercial) |
| JTAG (IEEE 1149.1) | Yes - in-system programming | — |
| Output Options | Totem-pole or open-drain (per pin) | — |
| Dedicated Inputs | 4 global inputs | — |
| RoHS 상태 | Non-RoHS (legacy SnPb finish typical) | Compliant (Pb-free "N" suffix) |
| 수명 주기 상태 | Obsolete (PDN effective 2017-06-01) | — |
| Macrocells | — | 128 |
| User I/Os | — | 84 |
| Propagation Delay (tPD) | — | 10 ns |
| Internal Frequency (fMAX) | — | 100 MHz |
| Supply Voltage (VCCINT) | — | 5 V |
| I/O Voltage (VCCIO) | — | 3.3 V or 5 V (MultiVolt) |
| Process Technology | — | CMOS EEPROM |
| In-System Programmability | — | Yes (IEEE 1149.1 JTAG) |
| 실장 유형 | — | Surface Mount |
| Lead-Free | — | Yes |