EPM7160STI100-10 vs EPM7160STI100-10N 비교
다음의 상세 나란히 비교: EPM7160STI100-10 제조: Altera 및 EPM7160STI100-10N 제조: Altera. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.
Altera
EPM7160STI100-10N - MAX 7000S CPLD, 160 Macrocells, 100MHz, TQFP-100 | Intel/Altera
EPM7160STI100-10N ⚠ 최종 구매사양 비교
| 파라미터 | EPM7160STI100-10 | EPM7160STI100-10N |
|---|---|---|
| 브랜드 | Altera | Altera |
| 카테고리 | FPGA & CPLD | FPGA & CPLD |
| 수명 주기 상태 | Obsolete | 최종 구매 |
| 재고 상태 | In Stock | In Stock |
| 단가 (USD) | $90.43 | $7.80 |
| Family | MAX 7000S | MAX 7000S |
| Macrocells | 160 | 160 |
| Usable Gates | 3,200 | 3200 |
| User I/Os | 84 | 84 (per Mouser listing; up to 104 per alternate datasheets) |
| Logic Elements / Blocks | 16 Logic Array Blocks (LABs) | — |
| Propagation Delay (tPD) | 10 ns | 10 ns |
| Maximum Operating Frequency | 100 MHz | — |
| Internal Supply Voltage | 4.75 V to 5.25 V | — |
| I/O Supply Voltage | 5.0 V | — |
| Programmable Type | In-System Programmable (EEPROM) | — |
| 동작 온도 | -40 C to +85 C (Industrial) | -40C to +85C (industrial, 'I' suffix) |
| 패키지 | TQFP-100 (100-pin Thin Quad Flat Pack) | — |
| 실장 유형 | Surface Mount | Surface Mount |
| JTAG / Boundary Scan | IEEE Std. 1149.1 compliant | — |
| PCI Compliance | PCI Local Bus Specification Rev. 2.2 (for -10 speed grade) | — |
| RoHS 상태 | [DATA_NEEDED: RoHS status - not explicitly stated in provided data] | — |
| MSL 레벨 | [DATA_NEEDED: MSL rating] | — |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Logic Blocks | — | 10 (LABs) |
| Internal Frequency | — | 100 MHz |
| Supply Voltage VCC | — | 5.0 V (3.3 V or 5 V tolerant I/O via MAX 7000S multi-voltage ISP) |
| Programmable Technology | — | EEPROM (non-volatile) |
| In-System Programmability | — | Yes (JTAG/IEEE 1149.1, 5.0V ISP) |
| Package Type | — | 100-pin TQFP (TQFP-100) |
| Lead-Free / RoHS | — | Yes (lead-free per 'I' industrial suffix) |
| Process Technology | — | CMOS, EEPROM-based |