EPM9560RC208-15 vs EPM9560RC208-10 비교

다음의 상세 나란히 비교: EPM9560RC208-15 제조: Altera 및 EPM9560RC208-10 제조: Intel. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.

사양 비교

파라미터 EPM9560RC208-15 EPM9560RC208-10
브랜드 Altera Intel
카테고리 FPGA & CPLD FPGA & CPLD
수명 주기 상태 Obsolete Obsolete
재고 상태 In Stock In Stock
단가 (USD) $0.00 $15.40
Family MAX 9000 MAX 9000
Device Type EEPROM-based Complex Programmable Logic Device (CPLD) CPLD (Complex Programmable Logic Device)
Usable Gates 12,000 gates 12,000
Macro Cells 560 macro cells —
Pin-to-Pin Delay 15 ns —
Counter Speed 117.6 MHz —
공급 전압 5.0 V —
Configuration Technology EEPROM (non-volatile) —
In-System Programmability Yes, via IEEE Std. 1149.1 JTAG —
패키지 208-pin RQFP (Power Quad Flat Pack) 208-pin RQFP (Plastic Quad Flat Pack)
실장 유형 Surface Mount Surface Mount
동작 온도 [DATA_NEEDED: operating temperature range] 0C to +70C (commercial)
Number of I/O Pins [DATA_NEEDED: number of I/O pins] —
Logic Array Blocks [DATA_NEEDED: number of logic array blocks] —
RoHS 상태 [DATA_NEEDED: RoHS status] [DATA_NEEDED: not stated in retrieved distributor listings]
Speed Grade -15 (15 ns pin-to-pin) —
Architecture Third-generation Multiple Array MatriX (MAX) —
Macrocells — 560
Logic Array Blocks (LABs) — 16
Maximum User I/O Pins — 212 (208-pin package variant)
Pin-to-Pin Delay (tPD) — 10 ns
Maximum Frequency (fMAX) — [DATA_NEEDED: internal toggle frequency in MHz]
Supply Voltage (VCCINT) — 5.0 V
I/O Standards Supported — 5.0 V TTL, 3.3 V LVTTL, 2.5 V (multiVolt I/O)
Configuration Memory — EEPROM (in-system programmable via JTAG)
Process Technology — 0.30 µm CMOS EEPROM
Lead-Free — [DATA_NEEDED: confirm lead-free status -10 suffix is conventional Pb-containing]
Programmability — JTAG (IEEE 1149.1) in-system programming

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