EPM9560RI304-15 vs EPM9560RCRC304-15 비교
다음의 상세 나란히 비교: EPM9560RI304-15 제조: Intel 및 EPM9560RCRC304-15 제조: Altera. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.
사양 비교
| 파라미터 | EPM9560RI304-15 | EPM9560RCRC304-15 |
|---|---|---|
| 브랜드 | Intel | Altera |
| 카테고리 | FPGA & CPLD | FPGA & CPLD |
| 수명 주기 상태 | NRND | Obsolete |
| 재고 상태 | In Stock | In Stock |
| 단가 (USD) | $112.00 | $0.00 |
| Device Family | MAX 9000 | MAX 9000 (EPM9560) |
| Architecture | Multiple Array MatriX (MAX) - EEPROM-based CPLD | Third-generation Multiple Array MatriX (MAX) |
| Macrocells | 560 | — |
| Flip-Flops | 772 | — |
| User I/Os | 212 (216 per some datasheets) | — |
| Dedicated Inputs | 4 | — |
| Total Terminals | 304 | — |
| Package Code | HFQFP / S-PQFP-G304 | — |
| Package Type | 304-pin RQFP (Quad Flat Pack, gull-wing) | — |
| Propagation Delay (tpd) | 11.4 ns (per digchip datasheet); 16.6 ns reported by MicrochipUSA | — |
| Maximum Internal Frequency | 145 MHz | — |
| Speed Grade | -15 | — |
| Supply Voltage (VCCINT/VCCIO) | 4.5 V to 5.5 V (5 V typical) | — |
| I/O Logic Levels | 3.3 V or 5 V configurable | — |
| 동작 온도 | 0 C to 70 C (commercial) | — |
| Temperature Grade | Industrial (per Partstack listings) | — |
| Logic Family | CMOS | — |
| Programming | 5.0-V in-system programmable via JTAG (IEEE 1149.1) | — |
| Process Technology | 0.5 µm CMOS EEPROM | — |
| 실장 유형 | Surface Mount | Surface Mount |
| RoHS 상태 | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Logic Type | — | EEPROM-based Complex Programmable Logic Device (CPLD) |
| Macro Cells | — | 560 |
| Usable Gates | — | 12,000 |
| Pin-to-Pin Propagation Delay (tPD) | — | 15 ns |
| Maximum Frequency | — | 117.6 MHz |
| 공급 전압 | — | 5.0 V |
| Configuration Memory | — | EEPROM (non-volatile, in-system programmable) |
| In-System Programmability (ISP) | — | Yes, via IEEE Std. 1149.1 JTAG |
| JTAG Interface | — | IEEE Std. 1149.1 (built-in) |
| 패키지 | — | 304-pin RQFP (PowerQuad Flat Pack) |
| 동작 온도 범위 | — | [DATA_NEEDED: operating temperature range] |
| Number of User I/O Pins | — | [DATA_NEEDED: user I/O pin count] |
| Logic Array Blocks (LABs) | — | [DATA_NEEDED: LAB count] |
| Lead Finish | — | [DATA_NEEDED: lead finish] |