KSZ8041MLL vs KSZ8081RNACA-TR 비교

다음의 상세 나란히 비교: KSZ8041MLL 제조: Microchip Technology 및 KSZ8081RNACA-TR 제조: Microchip Technology. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.

Microchip Technology
KSZ8041MLL KSZ8041MLL - 10/100 Ethernet PHY | Microchip | MII

KSZ8041MLL - 10/100 Ethernet PHY | Microchip | MII

KSZ8041MLL ✓ 활성
Microchip Technology
KSZ8081RNACA-TR KSZ8081RNACA-TR - 10/100 Ethernet PHY, RMII, 24-QFN | Microchip

KSZ8081RNACA-TR - 10/100 Ethernet PHY, RMII, 24-QFN | Microchip

KSZ8081RNACA-TR ✓ 활성

사양 비교

파라미터 KSZ8041MLL KSZ8081RNACA-TR
브랜드 Microchip Technology Microchip Technology
카테고리 Ethernet PHYs Interface ICs
수명 주기 상태 활성 활성
Ethernet Data Rate 10 Mb/s and 100 Mb/s —
Supported Physical Media 10BASE-T and 100BASE-TX —
Host Interface Full MII —
공급 전압 3.3 V —
Supply Configuration Single supply —
Transceiver Count 1 —
Port Count 1 Ethernet port —
패키지 48-LQFP 24-QFN (4x4 mm) with exposed pad
Package Body Size 7 mm x 7 mm —
핀 수 48 pins —
실장 유형 Surface mount Surface Mount
Automatic Crossover HP Auto MDI/MDIX —
Strapping Configuration Speed, duplex, auto-negotiation, power-down, and PHY address —
Strapping Latching Power-up and reset —
동작 온도 범위 [DATA_NEEDED: operating temperature range] —
Maximum Link Distance [DATA_NEEDED: maximum link distance] —
Power Consumption [DATA_NEEDED: power consumption] —
RoHS 상태 [DATA_NEEDED: RoHS status] Compliant
Product Type — 10/100BASE-TX Ethernet PHY Transceiver
인터페이스 — RMII v1.2 (Reduced Media Independent Interface)
Supply Voltage (VDDIO/VDDA) — 3.135 V to 3.465 V (3.3 V typical)
On-chip Core Voltage — 1.2 V (generated by internal LDO)
데이터 속도 — 10 Mbps / 100 Mbps (auto-negotiation)
Number of Transceivers — 1/1 (Full Duplex RMII)
Cable Type — CAT-3 / CAT-5 / CAT-5e UTP
Cable Reach — Up to 140 m (CAT-5)
Standards Compliance — IEEE 802.3, IEEE 802.3u
Reference Clock — 25 MHz crystal or 50 MHz RMII clock input
Management Interface — MDC/MDIO (SMI, IEEE 802.3u clause 22)
Auto-MDIX — Yes (HP Auto-MDIX)
동작 온도 — -40 C to +85 C (industrial)
MSL 레벨 — [DATA_NEEDED: MSL level]
Strap-in Pins — PHYAD[1:0], Config (latched at reset de-assertion)

데이터시트 & 자료

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