RTAX1000SL-CQ352V vs RTAX2000SL-1CQ352PROTO 비교

다음의 상세 나란히 비교: RTAX1000SL-CQ352V 제조: Microchip Technology 및 RTAX2000SL-1CQ352PROTO 제조: Microchip Technology. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.

Microchip Technology
RTAX1000SL-CQ352V RTAX1000SL-CQ352V - 1M-Gate Rad-Tolerant FPGA | Microchip

RTAX1000SL-CQ352V - 1M-Gate Rad-Tolerant FPGA | Microchip

RTAX1000SL-CQ352V ✓ 활성
Microchip Technology
RTAX2000SL-1CQ352PROTO RTAX2000SL-1CQ352PROTO - 2M-Gate Rad-Tolerant FPGA | Actel

RTAX2000SL-1CQ352PROTO - 2M-Gate Rad-Tolerant FPGA | Actel

RTAX2000SL-1CQ352PROTO ✓ 활성

사양 비교

파라미터 RTAX1000SL-CQ352V RTAX2000SL-1CQ352PROTO
브랜드 Microchip Technology Microchip Technology
카테고리 FPGA & CPLD FPGA & CPLD
수명 주기 상태 활성 활성
재고 상태 In Stock In Stock
단가 (USD) $0.00 $0.00
Family RTAX-SL (RTAX-S/SL Radiation-Tolerant FPGAs) RTAX-S/SL Radiation-Tolerant FPGAs
Equivalent System Gates 1,000,000 2,000,000
CLBs (Logic Modules) 12,096 —
Logic Cells 18,144 32,256
Maximum Toggle Frequency 581 MHz —
Process Technology 0.15 um CMOS CMOS, antifuse interconnect
Core Voltage 1.5 V [DATA_NEEDED: core supply voltage]
Programming Technology Antifuse (one-time programmable) —
Radiation Tolerance Radiation-tolerant, space-flight qualified family Radiation-tolerant (space-flight qualified family)
Power-Up Behavior Live at power-up (non-volatile) —
Configuration Upset Immunity No SEU in configuration memory (antifuse) —
Embedded Memory Embedded SRAM with built-in FIFO control logic Embedded SRAM with FIFO control logic
패키지 352-pin Ceramic CQFP (CQ352V) CQFP-352 (ceramic quad flat pack)
실장 유형 Surface Mount Surface Mount
동작 온도 [DATA_NEEDED: operating temperature range] [DATA_NEEDED: operating temperature range for PROTO variant]
I/O Voltage [DATA_NEEDED: I/O bank voltage range] [DATA_NEEDED: I/O supply voltage]
Total Ionizing Dose (TID) [DATA_NEEDED: TID rating in krad (Si)] —
MSL 레벨 [DATA_NEEDED: moisture sensitivity level] —
RoHS 상태 [DATA_NEEDED: RoHS compliance status] [DATA_NEEDED: RoHS status]
Estimated Equivalent Gates per CLB [DATA_NEEDED: gates-per-CLB ratio] —
Configurable Logic Blocks (CLBs) — 21,504
ASIC Gate Equivalent — 250,000
Terminal Pitch — 0.500 mm
Programmability — One-Time Programmable (antifuse, OTP)
Configuration — Live at power-up, single-chip
Variant Designation — PROTO (prototyping device)

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