SI5345A-D04594-GM vs SI5345A-D06546-GM 비교
다음의 상세 나란히 비교: SI5345A-D04594-GM 제조: Skyworks Solutions 및 SI5345A-D06546-GM 제조: Silicon Labs. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.
Skyworks Solutions
SI5345A-D04594-GM - 10-Output Jitter Attenuator | Skyworks
SI5345A-D04594-GM ✓ 활성Silicon Labs
SI5345A-D06546-GM - 10-Output Any-Freq Jitter Attenuator | Silicon Labs
SI5345A-D06546-GM ✓ 활성사양 비교
| 파라미터 | SI5345A-D04594-GM | SI5345A-D06546-GM |
|---|---|---|
| 브랜드 | Skyworks Solutions | Silicon Labs |
| 카테고리 | Clock & Timing | Clock & Timing |
| 수명 주기 상태 | 활성 | 활성 |
| 재고 상태 | In Stock | In Stock |
| 단가 (USD) | $25.90 | $14.20 |
| 기능 | 10-Channel Any-Frequency, Any-Output Jitter Attenuator / Clock Multiplier | Clock Multiplier / Jitter Attenuator |
| 출력 수 | 10 | 10 |
| Maximum Output Frequency | 1.028 GHz | — |
| Input Frequency Range | 10 MHz to 750 MHz (typical reference) | — |
| Output Formats | LVDS / LVPECL / HCSL / CML / CMOS (per-output programmable) | — |
| RMS Jitter | < 200 fs typical (12 kHz to 20 MHz integration) | — |
| Jitter Attenuation Bandwidth | Digitally programmable (0.1 Hz to 1 kHz range) | — |
| Core Supply Voltage | 1.8 V (typical) | 1.8 V or 3.3 V (single rail) [DATA_NEEDED: nominal typical] |
| Operating Supply Range | 1.71 V to 3.47 V | — |
| Configuration Interface | I2C / SPI (with on-chip NVM) | — |
| Reference Input | Crystal or single-ended/differential clock | Differential pair (XA/XB) |
| 패키지 | 64-VFQFN Exposed Pad (10x10 mm) | 64-pin QFN (10x10 mm) with exposed pad |
| 실장 유형 | Surface Mount | Surface Mount |
| 동작 온도 | -40 C to +85 C | -40C to +85C (industrial) [DATA_NEEDED: exact grade letter] |
| MSL 레벨 | 2 | [DATA_NEEDED: MSL rating] |
| RoHS 상태 | Compliant | Compliant |
| Max Output Frequency | — | 1028 MHz |
| Number of Inputs | — | 1 reference input pair (XA/XB) |
| Jitter (12 kHz to 20 MHz) | — | <200 fs RMS typical [DATA_NEEDED: exact figure] |
| Output Types Supported | — | LVPECL, LVDS, HCSL, CML, CMOS, SSTL (per-pin configurable) |
| Frequency Synthesis Range | — | 1 Hz to 1.028 GHz per output |
| Architecture | — | MultiSynth fractional-N DSPLL |
| Control Interface | — | I2C / SPI (ClockBuilder Pro configurable) |
| Lead Free | — | Yes |