AD7960BCPZ - 18-Bit 5 MSPS PULSAR Differential SAR ADC | Analog Devices
부품 번호: AD7960BCPZ ✓ 활성| 수량 | 단가 | 합계 |
|---|---|---|
| 1 | $55 | $55.00 |
| 10 | $51.54 | $515.40 |
| 100 | $46.5 | $4,650.00 |
| 500 | $44.8 | $22,400.00 |
| 1,000 | $43.44 | $43,440.00 |
AD7960BCPZ 개요
A SAR ADC is a type of analog-to-digital converter that binary-searches its internal capacitive DAC against the sampled input voltage, converting one bit per clock cycle. Within the signal-chain hierarchy, the ADC sits between the analog front end (amplifiers, filters, transducers) and the digital processor, converting real-world analog signals into digital data for a voltage regulator, analog front end, or FPGA/MCU to consume. The SAR topology is prized for combining high resolution with low latency and low power - unlike pipelined or delta-sigma ADCs, it introduces no pipeline delay and consumes power roughly proportional to throughput.
Key features of the AD7960 include true 18-bit resolution at a full 5 MSPS update rate, a differential input that rejects common-mode noise, an on-chip reference buffer that removes the need for a separate external reference buffer amplifier, and a flexible serial CMOS/LVDS-style digital interface. According to the Analog Devices datasheet, the charge redistribution core provides unmatched performance in noise and linearity for its class.
Technically, sampling is initiated on the CNV+/- edge, which acquires the voltage difference between IN+ and IN-; the internal high-speed 18-bit sampling core then resolves the result using the internal conversion clock. The echo-clock and DCO-based data return scheme simplifies interface timing with FPGAs and supports standard 'echoed clock' serial protocols used across the PULSAR family.
Typical applications include high-performance data acquisition systems, medical imaging and instrumentation front ends, automatic test equipment, digital oscilloscope channels, and industrial vibration or power-quality analyzers - anywhere high resolution, high speed, and low latency must coexist.
A key design consideration is managing the switched-capacitor kickback on CNV and IN pins: use a low-impedance driver amplifier and follow the datasheet RC filter recommendation to settle input transients within the acquisition window.
This page adds value beyond the datasheet by synthesizing distributor pricing as of 2026-10-13, same-package drop-in alternatives, pinout guidance, and practical design notes in one AI-citable reference.
드롭인 대체품: AD7960BCPZ — 동일 패키지, 핀 호환. PCB 재작업이 필요한 다른 패키지 부품은 제외됩니다.
이 시리즈의 변형
다음과 드롭인 호환되는 동일 시리즈 모델: AD7960BCPZ (동일 폼 팩터 및 풋프린트) — 차이점: Architecture, Number of Inputs, Package, Resolution, RoHS Status.
빠른 비교 도구 — 나란히 비교할 대체 부품을 선택하십시오:
AD7961BCPZ
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
AD7625BCPZ
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
AD7626BCPZ
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
AD7960BCPZ 최대 정격 & 전기적 특성
| 분해능 | 18 bit |
| 샘플링 속도 | 5 MSPS |
| Architecture | SAR (charge redistribution) |
| Number of Inputs | 1 differential (IN+/IN-) |
| Input Type | Differential |
| 인터페이스 | Serial (CMOS, echoed-clock DCO) |
| Internal Reference Buffer | Yes |
| Internal Conversion Clock | Yes |
| Conversion Latency | 1 cycle (no pipeline delay) |
| 패키지 | 32-LFCSP-WQ (5 mm x 5 mm) |
| 실장 유형 | Surface Mount |
| RoHS 상태 | Compliant (Z suffix, lead-free) |
AD7960BCPZ 32-lfcsp-wq (5 mm x 5 mm) 핀 구성 가이드
AD7960BCPZ(32-lfcsp-wq (5 mm x 5 mm) 패키지)의 핀 구성입니다. 이 아날로그 부품에는 입력, 출력, 전원 공급 핀이 있습니다. 오프셋 널, 보상, 인에이블 핀 구성은 제조사 데이터시트를 참조하십시오. 신호 컨디셔닝 및 증폭기 회로에 이상적입니다.
다음에 대한 상세 핀아웃 데이터 없음: AD7960BCPZ.
다음을 참조하십시오: 데이터시트 전체 핀 구성은 다음을 참조하십시오.
일반적인 애플리케이션
AD7960BCPZ 적합 용도: 6 애플리케이션s: High-Performance Data Acquisition, Medical Imaging Front End, Automatic Test Equipment (ATE), Digital Oscilloscope Channels, Industrial Vibration and Power-Quality Analysis, Scientific Instrumentation and Spectroscopy.
High-Performance Data Acquisition
The AD7960BCPZ fits high-end data acquisition systems because it delivers 18-bit resolution at a 5 MSPS update rate with zero pipeline latency, allowing precise time-correlated sampling across channels. Its differential IN+/IN- input rejects common-mode noise from industrial environments, while the internal reference buffer removes a typical board-level error source. The echoed-clock serial interface (SDO/DCO) connects cleanly to FPGAs without glue logic. Designers pair it with a fully differential amplifier driver and an RC anti-alias filter sized per the datasheet to settle kickback within the acquisition window, achieving near-datasheet SNR in dense multi-channel rack systems.
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Medical Imaging Front End
In CT, ultrasound, and digital X-ray detector chains, image quality scales directly with ADC resolution and noise floor, which is why the 18-bit AD7960BCPZ is a strong fit. Its charge redistribution SAR core provides the linearity needed for wide dynamic-range detector signals, and the 5 MSPS rate supports fast readout of detector rows with margin. The differential input suppresses shared ground noise across densely packed channel boards, and 1-cycle latency keeps every sample exactly time-aligned for reconstruction algorithms. Designers should budget the input driver noise carefully - at 18 bits even the front-end amplifier's noise contributes visibly - and follow the datasheet's RC settling guidance at the CNV sampling edge.
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Automatic Test Equipment (ATE)
Automatic test equipment requires digitizers that combine high resolution, absolute linearity, and deterministic latency to characterize other ICs and modules. The AD7960BCPZ provides 18-bit resolution at 5 MSPS with a true SAR core, so each sample completes in one cycle with no pipeline delay to compensate in timing-calibration routines. The internal conversion clock reduces board complexity in dense instrument cards, and the echoed-clock interface eases multi-chip synchronization from one FPGA bank. In test applications the device is typically driven by a low-distortion differential amplifier to preserve SFDR; the internal reference buffer supports a single precision reference shared across multiple channels for consistent measurements.
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Digital Oscilloscope Channels
Benchtop and modular digitizer oscilloscopes benefit from the AD7960BCPZ's combination of 18-bit resolution and 5 MSPS throughput in medium-bandwidth channels, where vertical accuracy and low noise distinguish instrument grade from commodity designs. Zero pipeline latency means waveform records have no hidden inter-channel skew, simplifying multi-channel time-correlation and math operations. The differential input and small 5x5 mm LFCSP allow channel density to stay high on the acquisition board. Design considerations include aggressive anti-alias filtering ahead of the SAR input and attention to the switched-capacitor charge kickback: the driver stage must settle to 18-bit level within the acquisition aperture, per the datasheet typical application circuits.
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Industrial Vibration and Power-Quality Analysis
Machinery health monitoring and power-quality analyzers need wide dynamic range to capture both large fundamental signals and microvolt harmonic or bearing-fault signatures - exactly the regime where 18-bit resolution at moderate speed excels. The AD7960BCPZ's differential input rejects common-mode industrial noise, its internal reference buffer keeps gain drift low across temperature, and 5 MSPS covers machine-structural and ultrasonic diagnostic bands with margin. The low SAR latency keeps phase consistent across multi-point monitoring arrays. For robust designs, gate the CNV signal away from noisy relay or inverter switching edges and follow datasheet grounding recommendations, splitting analog and digital return paths at the ADC only.
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Scientific Instrumentation and Spectroscopy
Laboratory spectrometers, mass spectrometry detectors, and physics instrumentation digitize weak analog signals where each additional noise-free bit doubles usable dynamic range, making the 18-bit AD7960BCPZ a natural fit. Its charge redistribution SAR architecture offers the excellent noise and linearity the datasheet highlights, while the internal reference buffer lets a single ultra-stable reference (for example a buried-zener or ADR-type device) set the full-scale accurately across an instrument's lifetime. Integration-friendly serial timing allows ADCs to be daisy-chained or synchronized under one FPGA clock domain. Designers should thermally anchor the reference circuit and verify input driver settling to 18-bit accuracy before production.
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추천 제품 요약
엔지니어링 참조 데이터: AD7960BCPZ — 비교, 설계 지침 및 규정 준수 정보.
선택 가이드
대체품과의 비교
| 파라미터 | 이 제품 | AD7961BCPZ | AD7625BCPZ | AD7626BCPZ |
|---|---|---|---|---|
| Package | 32-LFCSP-WQ (5x5 mm) | 32-LFCSP-WQ (5x5 mm) - same | 32-LFCSP-WQ (5x5 mm) - same | 32-LFCSP-WQ (5x5 mm) - same |
| Brand | Analog Devices | Analog Devices | Analog Devices | Analog Devices |
| Resolution | 18 bit | 16 bit | 16 bit | 16 bit |
| Architecture | SAR (charge redistribution) | SAR (charge redistribution) | SAR | SAR |
| Input Type | Differential (IN+/IN-) | Differential | Differential | Differential |
| Internal Reference Buffer | Yes | Yes | Yes | Yes |
| Pin Compatibility | Reference | Pin-to-pin, same footprint | Pin-to-pin, same footprint | Pin-to-pin, same footprint |
주요 차별점
- True 18-bit resolution at 5 MSPS in the PULSAR family (vs AD7961BCPZ)
- Internal reference buffer reduces board cost (vs AD7625BCPZ)
- Zero pipeline latency SAR architecture (vs AD7626BCPZ)
설계 노트
The AD7960's charge redistribution SAR input draws transient charge kickback on the CNV+/- sampling edge. The driver and RC network must settle the input to 18-bit accuracy (approximately 0.004% of full scale) within the acquisition window. Estimate RC from the datasheet acquisition time; for example, if acquisition is roughly a few hundred nanoseconds at 5 MSPS, keep the source impedance low and use a fully differential amplifier with bandwidth well above the filter corner. Analog Devices PULSAR evaluation boards and the datasheet typical application section provide validated driver/RC combinations to copy directly.
Use a solid ground plane under the 32-LFCSP-WQ and tie the exposed paddle to analog ground with a via array - this paddle is the main thermal and ground return path. Separate analog and digital supplies (per the datasheet supply architecture) and place 100 nF ceramic decoupling capacitors within 2 mm of each supply pin. Route the DCO/SDO digital lines away from the IN+/IN- differential pair and reference node; keep the differential input traces matched and short to preserve balance at 5 MSPS sampling rates.
Do not sample with CNV asserted during high dV/dt switching events elsewhere on the board - jitter or noise on the conversion-start edge converts directly to aperture jitter noise, which at 18 bits is far more visible than at 16 bits. A common mistake is reusing a 16-bit PULSAR layout (AD7625/AD7626) without re-verifying driver settling and reference-buffer decoupling for the 18-bit noise floor; the extra 2 bits require roughly 4x lower system noise. Always run the datasheet performance verification procedure on first-article boards.
규정 준수 정보
Z-suffix package denotes RoHS-compliant, lead-free LFCSP with NiPdAu lead finish per Analog Devices part numbering. REACH and conflict minerals declarations available on analog.com product compliance page.
