AD9226AST - 12-Bit 65-MSPS ADC | Analog Devices
부품 번호: AD9226AST ✗ 단종| 수량 | 단가 | 합계 |
|---|---|---|
| 1 | $0 | $0.00 |
| 10 | $0 | $0.00 |
| 100 | $0 | $0.00 |
| 500 | $0 | $0.00 |
| 1,000 | $0 | $0.00 |
AD9226AST 개요
An ADC is an analog-to-digital converter, a data-acquisition IC that samples a continuous analog voltage and represents each sample with a digital code. The AD9226 belongs to the pipeline ADC hierarchy, which uses multistage conversion to support high sampling rates and parallel digital outputs. Its 12-bit resolution provides 4096 possible code levels, while the 65-MSPS rate suits communications, instrumentation, and intermediate-frequency signal chains.
The core verified features include a 12-bit resolution, one pipelined differential input, 65 MSPS operation, and integrated sample-and-hold and reference functions. The manufacturer's datasheet also describes undersampling schemes for single-channel communications. Additional performance figures in the provided search material include ENOB of 11.1 bits at a 10 MHz input, intermodulation distortion below -75 dBFS at a 140 MHz input, and guaranteed no-missing-codes operation, though complete test conditions must be taken from the manufacturer datasheet.
The AD9226AST uses a single-supply architecture and differential pipeline conversion. Differential signaling helps reduce sensitivity to common-mode noise, while the parallel digital outputs require a correctly timed receiver and controlled PCB routing. Because this is an older high-speed data converter, signal integrity, supply decoupling, clock quality, and output-bus timing are as important as nominal resolution.
Typical uses include digital communications receivers, IF undersampling front ends, industrial measurement systems, and instrumentation requiring 12-bit conversion rates up to 65 MSPS. A suitable design should provide a low-jitter sampling clock, matched input-network values, solid reference and supply bypassing, and controlled impedance for high-speed digital traces.
The principal design trade-off is throughput versus resolution: 65 MSPS is useful for wideband or undersampled signals, but 12-bit conversion does not provide the precision of higher-resolution ADCs. Confirm input bandwidth, analog range, output timing, and package-level land-pattern requirements against the manufacturer datasheet before production release.
This page combines verified manufacturer and distributor information with application guidance, compatibility cautions, and source-linked technical context. Pricing, stock, lifecycle status, and full pin-level data are not stated in the supplied records and therefore are not inferred here.
드롭인 대체품: AD9226AST — 동일 패키지, 핀 호환. PCB 재작업이 필요한 다른 패키지 부품은 제외됩니다.
이 시리즈의 변형
다음과 드롭인 호환되는 동일 시리즈 모델: AD9226AST (동일 폼 팩터 및 풋프린트) — 차이점: Package, ADC Type, Intermodulation Distortion, Operating Temperature, RoHS Status.
빠른 비교 도구 — 나란히 비교할 대체 부품을 선택하십시오:
AD9226ASTZ
✅ 드롭인✓ 재고 있음
$61.056 / 개
데이터시트 보기 →AD9226ASTZRL
✅ 드롭인✓ 재고 있음
가격 문의
데이터시트 보기 →AD9226AST 최대 정격 & 전기적 특성
| ADC Type | Pipeline ADC |
| 분해능 | 12 bit |
| 샘플링 속도 | 65 MSPS |
| Number of Inputs | 1 input |
| Input Architecture | Differential pipelined |
| Supply Configuration | Single supply |
| Sample-and-Hold Amplifier | On-chip |
| Voltage Reference | On-chip |
| ENOB | 11.1 bit at 10 MHz input |
| Intermodulation Distortion | -75 dBFS or better at 140 MHz input |
| No Missing Codes | Guaranteed |
| 패키지 | 48-LQFP (7 mm x 7 mm) |
| 핀 수 | 48 pins |
| 실장 유형 | Surface mount |
AD9226AST 48-lqfp (7 mm x 7 mm) 핀 구성 가이드
AD9226AST(48-lqfp (7 mm x 7 mm) 패키지)의 핀 구성입니다. 이 아날로그 부품에는 입력, 출력, 전원 공급 핀이 있습니다. 오프셋 널, 보상, 인에이블 핀 구성은 제조사 데이터시트를 참조하십시오. 신호 컨디셔닝 및 증폭기 회로에 이상적입니다.
다음에 대한 상세 핀아웃 데이터 없음: AD9226AST.
다음을 참조하십시오: 데이터시트 전체 핀 구성은 다음을 참조하십시오.
일반적인 애플리케이션
AD9226AST 적합 용도: 6 애플리케이션s: Digital Communications IF Receiver, Wideband Instrumentation Front End, Industrial Vibration and Transient Capture, RF and Microwave Signal Analysis, High-Speed Data Acquisition, Telecommunications Baseband Processing.
Digital Communications IF Receiver
The AD9226AST is a 12-bit, 65-MSPS pipeline ADC designed for high-rate signal acquisition, including the IF undersampling schemes highlighted by Analog Devices. Place it behind the receiver's RF or mixer stage when the desired intermediate frequency can be sampled directly and aliased into the digital bandwidth. Its 11.1-bit ENOB at a 10 MHz input provides a useful starting point for link-budget and demodulation simulations. The design must verify analog input bandwidth, allowable aliasing, clock jitter, differential input impedance, and output timing before fixing the IF plan.
추천
Wideband Instrumentation Front End
Use the AD9226AST when an instrumentation channel must acquire waveforms at up to 65 MSPS while retaining 12-bit digital resolution. Its on-chip sample-and-hold amplifier and voltage reference reduce the number of external converter blocks, allowing the analog front end to concentrate on gain, bandwidth, anti-alias filtering, and input coupling. The verified 11.1-bit ENOB at 10 MHz is a concrete dynamic-performance reference, not a blanket guarantee at every frequency. Validate full-scale range, source impedance, clock jitter, and acquisition timing against the instrument's measurement bandwidth.
추천
Industrial Vibration and Transient Capture
The AD9226AST can capture short industrial transients when sampling speed matters more than ultra-high resolution. A 65-MSPS conversion rate allows waveform features to be represented with 12-bit codes, while the differential input architecture helps reject common-mode noise when the source and converter share a carefully controlled reference. The converter should be paired with a suitable sensor amplifier, protection network, and anti-alias filter. Check the industrial temperature grade, isolation strategy, vibration profile, and calibration requirements in the exact ordering documentation.
추천
RF and Microwave Signal Analysis
For RF and microwave test systems, the AD9226AST is appropriate when a 65-MSPS, 12-bit converter can represent the selected intermediate-frequency content. Analog Devices specifically describes the sample-and-hold amplifier as suitable for undersampling beyond Nyquist-related signal paths, enabling a compact receiver stage without first converting the signal to a lower frequency. The system designer must still calculate alias placement, spectral image rejection, analog gain, and clock-jitter limits. The supplied record reports intermodulation distortion of -75 dBFS or better at 140 MHz, providing a useful benchmark for front-end planning.
추천
High-Speed Data Acquisition
The AD9226AST fits a compact high-speed data-acquisition module when each channel must sample at up to 65 MSPS and the system can tolerate 12-bit resolution rather than laboratory-grade accuracy. Its monolithic converter combines sampling and reference functions, reducing the number of discrete components in the analog front end. The module should include controlled-impedance routing for digital outputs, a low-noise clock distribution network, local decoupling, and an FPGA or DSP capable of receiving the converter's timing. Confirm output format and voltage levels from the manufacturer datasheet before selecting the receiver logic.
추천
Telecommunications Baseband Processing
The AD9226AST can serve as the conversion stage in a telecommunications receiver when a 12-bit code width and 65-MSPS throughput match the baseband design. Differential analog signaling, an integrated sample-and-hold amplifier, and an integrated reference help simplify the converter interface, while the multistage pipeline supports high-rate acquisition. Engineers should budget for clock jitter, input full-scale range, filtering, quantization noise, and downstream digital timing. The verified product material does not specify a particular protocol, so the ADC choice must be validated against the system's modulation, channel bandwidth, and required carrier-to-noise performance.
추천
추천 제품 요약
엔지니어링 참조 데이터: AD9226AST — 비교, 설계 지침 및 규정 준수 정보.
선택 가이드
대체품과의 비교
| 파라미터 | 이 제품 | AD9226ASTZ | AD9226ASTZRL |
|---|---|---|---|
| Brand | Analog Devices | Analog Devices | Analog Devices |
| Resolution | 12 bit | 12 bit | 12 bit |
| Sampling Rate | 65 MSPS | 65 MSPS | 65 MSPS |
주요 차별점
- High sampling throughput in a 12-bit converter (vs AD9226ASTZ)
- Integrated sampling and reference functions (vs AD9226ASTZRL)
- Undersampling-oriented signal capture (vs AD9226ASTZ)
설계 노트
The supplied data confirms a 65-MSPS differential pipeline ADC and IF undersampling use, so treat the analog input and clock paths as high-speed controlled-impedance structures. Keep the differential pair symmetric, minimize stubs and unnecessary vias, and place input protection and filtering components where their parasitics can be included in the frequency plan. Verify the complete input network against the manufacturer's recommended application circuit rather than relying only on nominal ADC resolution.
Place the analog, reference, and supply bypassing components immediately at their associated device pins. Use a short, low-inductance return path and keep high-current digital return currents away from the sample-and-hold and reference regions. The supplied records identify an integrated sample-and-hold amplifier and voltage reference, but do not specify the official recommended capacitor values; obtain those values from the AD9226 datasheet before finalizing the PCB.
Do not select AD9226ASTZ or AD9226ASTZRL as a drop-in substitute solely because the search results show the same AD9226 family and a 48-LQFP package. Confirm pin assignments, temperature grade, supply limits, timing, output mapping, lifecycle status, and manufacturer-approved ordering codes. Also verify clock jitter and source impedance: a 12-bit nominal resolution does not guarantee 12-bit effective performance in an inadequately conditioned signal chain.
규정 준수 정보
The supplied manufacturer and distributor search results do not state RoHS, REACH, lead-free, halogen-free, conflict-minerals, or AEC-Q100 status for AD9226AST. Confirm the exact ordering code with Analog Devices documentation.