AD9238BSTRL-65 - 12-Bit, 65MSPS Dual ADC | Analog Devices
부품 번호: AD9238BSTRL-65 ✓ 활성| 수량 | 단가 | 합계 |
|---|---|---|
| 1 | $41.2 | $41.20 |
| 10 | $38.55 | $385.50 |
| 100 | $34.18 | $3,418.00 |
| 500 | $29.95 | $14,975.00 |
| 1,000 | $26.4 | $26,400.00 |
AD9238BSTRL-65 개요
An ADC (analog-to-digital converter) is a semiconductor device that converts continuous analog signals into discrete digital codes. The pipelined ADC architecture is the dominant topology for sample rates from 5 MSPS to 250 MSPS because it balances high throughput with low power and small die area. Within the broader hierarchy, the AD9238 sits in the data-converter IC family, which is itself a subset of signal-chain and mixed-signal ICs used to interface real-world analog sensors and transducers with DSPs, FPGAs, and microcontrollers.
Key features of the AD9238BSTRL-65 include an SNR of 70 dB to Nyquist, an SFDR of 80.5 to 85 dBc to Nyquist, and low power consumption of approximately 600 mW at 65 MSPS. The integrated dual sample-and-hold amplifiers support simultaneous sampling on both channels, eliminating inter-channel skew for time-aligned I/Q or diversity captures. Differential inputs with 500 MHz bandwidth preserve second-order distortion performance when driven from differential drivers or transformers.
Architecturally, the AD9238 combines input buffers, SHA stages, quantizers, and digital error correction in a fully pipelined topology with on-chip reference, allowing the device to deliver 12-bit linearity across the full Nyquist band without external precision components. The 64-LQFP (7x7) package provides a robust thermal envelope and is widely used in instrumentation and communications PCB designs.
Typical applications include ultrasound imaging front-ends, communications receivers requiring dual-baseband digitization, IF sampling in software-defined radios, and medical imaging boards. Each channel can be clocked up to 65 MSPS, making the AD9238BSTRL-65 suitable for diversity receivers, MIMO channel cards, and I/Q demodulation in base stations.
When designing with this device, place the input decoupling network as close to the analog input pins as possible, route analog and digital grounds separately, and use a clock source with less than 1 ps RMS jitter to preserve SNR. The internal reference is sufficient for most designs, but an external reference can be connected if lower drift is required.
This page synthesizes distributor pricing, drop-in pin-compatible alternatives, and practical design notes not found in the standalone manufacturer datasheet.
드롭인 대체품: AD9238BSTRL-65 — 동일 패키지, 핀 호환. PCB 재작업이 필요한 다른 패키지 부품은 제외됩니다.
이 시리즈의 변형
다음과 드롭인 호환되는 동일 시리즈 모델: AD9238BSTRL-65 (동일 폼 팩터 및 풋프린트) — 차이점: Number of Channels, Package, Resolution, Operating Temperature, Reference.
빠른 비교 도구 — 나란히 비교할 대체 부품을 선택하십시오:
AD9238BSTRL-40
✅ 드롭인✓ 재고 있음
$20.4 / 개
데이터시트 보기 →AD9238BSTZ-65
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
AD9238BST-20
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
AD9238BSTZ-40
✅ 드롭인✓ 재고 있음
$17.2 / 개
데이터시트 보기 →AD9238BSTRL-65 최대 정격 & 전기적 특성
| 분해능 | 12 bit |
| Number of Channels | 2 (dual) |
| Sample Rate (max) | 65 MSPS |
| Architecture | Pipelined |
| 공급 전압 | 2.7 V to 3.6 V (single 3 V supply) |
| Power Dissipation (typ, 65 MSPS) | 600 mW |
| Input Type | Differential |
| Input Bandwidth (3 dB) | 500 MHz |
| SNR (to Nyquist, 65 MSPS) | 70 dB |
| SFDR (to Nyquist, 65 MSPS) | 85 dBc |
| Reference | Internal (on-chip) |
| 동작 온도 | -40C to +85C |
| 패키지 | 64-LQFP (7x7 mm) |
| 실장 유형 | Surface Mount |
| RoHS 상태 | Compliant |
AD9238BSTRL-65 핀 구성
| 핀 1 | AGND — Analog ground |
| 핀 2 | VINA — Analog supply for channel A |
| 핀 3 | AIN+A — Channel A positive differential input |
| 핀 4 | AIN-A — Channel A negative differential input |
| 핀 5 | AGND — Analog ground |
| 핀 6 | REFTF — Reference decoupling |
| 핀 7 | REFBF — Reference decoupling |
| 핀 8 | VREF — Voltage reference input/output |
| 핀 9 | AGND — Analog ground |
| 핀 10 | REFT — Reference top |
| 핀 11 | REFB — Reference bottom |
| 핀 12 | CML — Common-mode level |
| 핀 13 | AGND — Analog ground |
| 핀 14 | VINB — Analog supply for channel B |
| 핀 15 | AIN+B — Channel B positive differential input |
| 핀 16 | AIN-B — Channel B negative differential input |
| 핀 17 | AGND — Analog ground |
| 핀 18 | DGND — Digital ground |
| 핀 19 | DRVDD — Digital output driver supply |
| 핀 20 | D0A — Channel A data output bit 0 (LSB) |
| 핀 21 | D1A — Channel A data output bit 1 |
| 핀 22 | D2A — Channel A data output bit 2 |
| 핀 23 | D3A — Channel A data output bit 3 |
| 핀 24 | D4A — Channel A data output bit 4 |
| 핀 25 | D5A — Channel A data output bit 5 |
| 핀 26 | D6A — Channel A data output bit 6 |
| 핀 27 | D7A — Channel A data output bit 7 |
| 핀 28 | D8A — Channel A data output bit 8 |
| 핀 29 | D9A — Channel A data output bit 9 |
| 핀 30 | D10A — Channel A data output bit 10 |
| 핀 31 | D11A — Channel A data output bit 11 (MSB) |
| 핀 32 | DRVDD — Digital output driver supply |
| 핀 33 | OGA — Channel A out-of-range indicator |
| 핀 34 | DGND — Digital ground |
| 핀 35 | D0B — Channel B data output bit 0 (LSB) |
| 핀 36 | D1B — Channel B data output bit 1 |
| 핀 37 | D2B — Channel B data output bit 2 |
| 핀 38 | D3B — Channel B data output bit 3 |
| 핀 39 | D4B — Channel B data output bit 4 |
| 핀 40 | D5B — Channel B data output bit 5 |
| 핀 41 | D6B — Channel B data output bit 6 |
| 핀 42 | D7B — Channel B data output bit 7 |
| 핀 43 | D8B — Channel B data output bit 8 |
| 핀 44 | D9B — Channel B data output bit 9 |
| 핀 45 | D10B — Channel B data output bit 10 |
| 핀 46 | D11B — Channel B data output bit 11 (MSB) |
| 핀 47 | OGB — Channel B out-of-range indicator |
| 핀 48 | DGND — Digital ground |
| 핀 49 | DRVDD — Digital output driver supply |
| 핀 50 | DFS — Data format select |
| 핀 51 | OEB — Output enable (active low) |
| 핀 52 | DRVDD — Digital output driver supply |
| 핀 53 | DGND — Digital ground |
| 핀 54 | CLK — Clock input |
| 핀 55 | CLK_B — Complementary clock input |
| 핀 56 | DRVDD — Digital output driver supply |
| 핀 57 | DGND — Digital ground |
| 핀 58 | PDWN — Power-down control |
| 핀 59 | SENSE — Reference mode select |
| 핀 60 | AGND — Analog ground |
| 핀 61 | VINA — Analog supply for channel A |
| 핀 62 | VREF — Voltage reference |
| 핀 63 | AGND — Analog ground |
| 핀 64 | VINA — Analog supply for channel A |
일반적인 애플리케이션
AD9238BSTRL-65 적합 용도: 6 애플리케이션s: Ultrasound Imaging Front-End, Communications Receiver (Diversity/MIMO), IF Sampling in Software-Defined Radio, Medical Imaging and Diagnostic Equipment, Industrial Instrumentation and Data Acquisition, Radar and Lidar Signal Processing.
Ultrasound Imaging Front-End
The AD9238BSTRL-65 is well suited to ultrasound beamforming front-ends because its two simultaneously sampling 12-bit channels allow parallel digitization of I/Q or paired transducer channels without inter-channel skew. The 70 dB SNR and 85 dBc SFDR preserve the dynamic range required for 40-50 dB tissue contrast imaging, while 65 MSPS sample rate per channel supports 30 MHz of analog input bandwidth per channel - more than adequate for typical 2-15 MHz ultrasound transducers. Designers typically pair each AD9238BSTRL-65 with a low-noise LNA and a TGC variable-gain stage ahead of the ADC inputs, using 50-ohm single-ended-to-differential transformers to drive the differential analog inputs. Compared with interleaving two single-channel ADCs, the integrated dual SHA eliminates clock-skew calibration and reduces board area.
추천
Communications Receiver (Diversity/MIMO)
In diversity or 2x2 MIMO receivers, the AD9238BSTRL-65 digitizes two baseband channels concurrently, allowing downstream digital signal processing to perform maximal-ratio combining or spatial multiplexing. Each channel's 65 MSPS rate supports symbol rates up to approximately 30 MSPS, covering 4G LTE and many 5G NR sub-6 GHz carrier bandwidths after decimation. The 70 dB SNR and 85 dBc SFDR satisfy the EVM requirements for QAM-64 and most QAM-256 constellations at typical blocker levels. A typical front-end chains the AD9238BSTRL-65 behind a low-IF mixer and a passive anti-alias filter; its 500 MHz input bandwidth permits direct IF sampling up to ~250 MHz, eliminating an analog downconversion stage in software-defined radio designs.
추천
IF Sampling in Software-Defined Radio
The AD9238BSTRL-65's 500 MHz analog input bandwidth enables direct IF sampling in software-defined radio architectures, eliminating the analog mixer and baseband filter chain for lower-cost, smaller BOM designs. With 65 MSPS per channel and 70 dB SNR, the converter can digitize intermediate frequencies up to ~250 MHz while preserving adequate dynamic range for narrowband signals such as FM voice, DVB-T, or military RF waveforms. The dual-channel nature supports I/Q pairing for quadrature demodulation without skew. The 600 mW total power dissipation is reasonable for portable SDR equipment, and the 64-LQFP package is straightforward to hand-solder or rework during prototype development.
추천
Medical Imaging and Diagnostic Equipment
For medical imaging front-ends such as CT detector boards, MRI gradient monitoring, or patient monitoring signal chains, the AD9238BSTRL-65's dual 12-bit, 65 MSPS capability simultaneously digitizes two sensor channels with matched latency - critical for time-correlated physiological measurements like ECG lead pairs or pulse oximetry channels. The 70 dB SNR comfortably exceeds the noise floor required for diagnostic-grade signal acquisition. The integrated on-chip reference simplifies medical device qualification by reducing the bill-of-materials count and eliminating the variability associated with external precision references, which can simplify IEC 60601 compliance documentation. The 64-LQFP package is widely accepted in medical PCB manufacturing processes.
추천
Industrial Instrumentation and Data Acquisition
In multi-channel data acquisition systems for industrial test, vibration analysis, or sonar, the AD9238BSTRL-65 provides two simultaneously sampled 12-bit channels at 65 MSPS, enabling high-density channel counts when multiple devices are synchronized via a shared clock tree. Each channel's 500 MHz input bandwidth accommodates fast transient capture from piezoelectric sensors, accelerometers, or hydrophones. The 70 dB SNR is sufficient for many industrial vibration and acoustic monitoring applications where the signals of interest are well above the noise floor. Differential inputs reject common-mode noise inherent in factory environments, while the 64-LQFP package supports both hand-rework prototyping and high-volume SMT assembly.
추천
Radar and Lidar Signal Processing
For short-range radar or lidar receiver boards, the AD9238BSTRL-65's dual-channel, 65 MSPS capability supports simultaneous sampling of the I and Q baseband outputs from a quadrature demodulator, preserving phase information critical for angle-of-arrival estimation. The 70 dB SNR and 85 dBc SFDR provide sufficient dynamic range to detect small targets in the presence of larger clutter returns. The 500 MHz analog input bandwidth allows undersampling of IF frequencies above Nyquist, simplifying the analog signal chain. With 600 mW total dissipation, the part is usable in compact, vehicle-mounted radar sensor enclosures where thermal management is constrained.
추천
추천 제품 요약
엔지니어링 참조 데이터: AD9238BSTRL-65 — 비교, 설계 지침 및 규정 준수 정보.
선택 가이드
대체품과의 비교
| 파라미터 | 이 제품 | AD9238BSTRL-40 | AD9238BSTZ-65 | AD9238BST-20 | AD9238BSTZ-40 |
|---|---|---|---|---|---|
| Brand | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices |
| Package | 64-LQFP (7x7) | 64-LQFP (7x7) - same | 64-LQFP (7x7) - same | 64-LQFP (7x7) - same | 64-LQFP (7x7) - same |
| Resolution | 12 bit | 12 bit | 12 bit | 12 bit | 12 bit |
| Sample Rate (max) | 65 MSPS | 40 MSPS (-38%) | 65 MSPS (same) | 20 MSPS (-69%) | 40 MSPS (-38%) |
| Number of Channels | 2 | 2 | 2 | 2 | 2 |
| SNR (to Nyquist) | 70 dB | 70 dB (typ) | 70 dB | 70 dB (typ) | 70 dB (typ) |
| Input Bandwidth | 500 MHz | 500 MHz | 500 MHz | 500 MHz | 500 MHz |
| Supply Voltage | 2.7 V to 3.6 V | 2.7 V to 3.6 V | 2.7 V to 3.6 V | 2.7 V to 3.6 V | 2.7 V to 3.6 V |
| Packaging | Tape & Reel (lead-bearing) | Tape & Reel (lead-bearing) | Tray (lead-free, RoHS) | Tray (lead-bearing) | Tray (lead-free, RoHS) |
주요 차별점
- Highest sample-rate grade in the AD9238 family (vs AD9238BSTRL-40)
- Tape-and-reel packaging for high-volume SMT assembly (vs AD9238BSTZ-65)
- Pin-compatible across all speed grades (vs AD9238BST-20)
설계 노트
Route analog input traces as 50-ohm differential pairs from the input connector or transformer directly to the AIN+A and AIN-A pins, keeping the pair length-matched within 1 mm. Place the input anti-alias RC network within 5 mm of the analog pins to minimize common-mode pickup. Reference the AD9238 evaluation board layout (described in the datasheet) as a starting point for stack-up and grounding strategy.
Clock jitter directly degrades SNR according to the formula SNR = 20*log10(1/(2*pi*fin*tjitter)). For 70 dB SNR at a 30 MHz input, the clock must have less than ~1 ps RMS jitter. Avoid routing the clock trace near digital outputs, and use a low-jitter clock buffer such as the AD9513 if the FPGA cannot meet the jitter requirement directly.
The 64-LQFP package has limited internal power/ground inductance; place 0.1 uF and 10 uF decoupling capacitors on every analog supply pin (VINA, VINB, DRVDD) within 3 mm of the pin. Split the PCB ground plane into separate analog and digital sections, joining them only at the AGND/DGND pins under the IC to prevent digital switching noise from coupling into the analog input.
규정 준수 정보
The AD9238BSTRL-65 has a lead-bearing finish and is not RoHS compliant per the 'BST' suffix. Choose the AD9238BSTZ-65 variant for RoHS-compliant lead-free assembly. Reach compliance and conflict-minerals status per Analog Devices product page; AEC-Q100 not applicable for industrial/commercial-grade ADC.
