AD9280ARSRL - 8-Bit 32 MSPS CMOS ADC | Analog Devices
부품 번호: AD9280ARSRL ✓ 활성| 수량 | 단가 | 합계 |
|---|---|---|
| 1 | $5.15 | $5.15 |
| 10 | $4.62 | $46.20 |
| 100 | $4.13 | $413.00 |
| 500 | $3.7 | $1,850.00 |
| 1,000 | $3.32 | $3,320.00 |
| 2,500 | $2.95 | $7,375.00 |
AD9280ARSRL 개요
What is a pipelined CMOS ADC? A pipelined analog-to-digital converter is a high-speed data converter architecture that processes the analog input through multiple low-resolution stage ADCs in series, with each stage handling a portion of the conversion before passing a residue to the next stage. Pipelined ADCs sit within the broader hierarchy of ADC -> data converter -> mixed-signal IC -> semiconductor, and are the dominant architecture for sampling rates between roughly 10 MSPS and several hundred MSPS where successive-approximation (SAR) converters become too slow and flash converters become impractical. The on-chip sample-and-hold (SHA) front-end and integrated voltage reference are critical to eliminating external component count and simplifying PCB layout at high frequencies.
Key features of the AD9280ARSRL include a pin-compatible upgrade path from the legacy AD876-8, differential nonlinearity (DNL) of 0.2 LSB, a power-down (sleep) mode for battery-powered applications, three-state outputs for bus sharing, and an out-of-range indicator that flags overranged input conditions. The 300 MHz onboard sample-and-hold amplifier can be configured for either single-ended or differential inputs, providing flexibility for direct-IF sampling or baseband signal acquisition.
The AD9280 uses a multistage differential pipeline architecture, which provides inherent latency of several clock cycles but enables the 32 MSPS conversion rate without the power penalty of flash architectures. Internal registers and the proprietary reference design eliminate the need for external reference components, while the integrated SHA relaxes the input driver bandwidth requirement.
Typical applications include video digitizers, CCD/camera imaging front-ends, digital oscilloscope front-ends, IF sampling in communication receivers, medical imaging, and low-cost consumer digital still cameras. The wide supply range supports both 3 V portable designs and 5 V industrial platforms.
When designing with this ADC, ensure the analog input is driven by a low-impedance, bandwidth-appropriate buffer; the SHA 3 dB corner frequency must be considered when using the high-pass-coupling configuration. The three-state output mode requires careful bus-arbiter logic to prevent contention when multiple converters share a data bus.
This page synthesizes distributor pricing, drop-in alternatives from the same AD9280 family and pin-compatible competitors, and practical design notes not found in the standalone datasheet.
드롭인 대체품: AD9280ARSRL — 동일 패키지, 핀 호환. PCB 재작업이 필요한 다른 패키지 부품은 제외됩니다.
이 시리즈의 변형
다음과 드롭인 호환되는 동일 시리즈 모델: AD9280ARSRL (동일 폼 팩터 및 풋프린트) — 차이점: Architecture, Sampling Rate, Supply Voltage.
빠른 비교 도구 — 나란히 비교할 대체 부품을 선택하십시오:
AD9280ARSZ
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
AD9280ARSZRL
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
AD9280ARS
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
AD9280ARSR
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
AD876-8ARSRL
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
AD9280ARSRL 최대 정격 & 전기적 특성
| 분해능 | 8 bits |
| 샘플링 속도 | 32 MSPS |
| Number of Channels | 1 |
| Architecture | Pipelined CMOS |
| 공급 전압 | 2.7 V to 5.5 V (single supply) |
| Power Dissipation | 95 mW at 3 V supply |
| Differential Nonlinearity (DNL) | 0.2 LSB |
| On-chip Sample-and-Hold Bandwidth | 300 MHz |
| Input Configuration | Single-ended or differential |
| On-chip Voltage Reference | Yes (internal) |
| Output Interface | Parallel, three-state outputs |
| Out-of-Range Indicator | Yes |
| Power-Down (Sleep) Mode | Yes |
| Pin Compatibility | Pin-compatible with AD876-8 |
| 패키지 | 28-pin SSOP |
| RoHS 상태 | Compliant (per DigiKey listing) |
AD9280ARSRL 28-pin ssop 핀 구성 가이드
AD9280ARSRL(28-pin ssop 패키지)의 핀 구성입니다. 이 아날로그 부품에는 입력, 출력, 전원 공급 핀이 있습니다. 오프셋 널, 보상, 인에이블 핀 구성은 제조사 데이터시트를 참조하십시오. 신호 컨디셔닝 및 증폭기 회로에 이상적입니다.
다음에 대한 상세 핀아웃 데이터 없음: AD9280ARSRL.
다음을 참조하십시오: 데이터시트 전체 핀 구성은 다음을 참조하십시오.
일반적인 애플리케이션
AD9280ARSRL 적합 용도: 6 애플리케이션s: Video Digitizer Front-End, CCD/Camera Imaging Front-End, Digital Oscilloscope Front-End, IF Sampling in Communication Receivers, Medical Ultrasound Imaging, Industrial Process Control Data Acquisition.
Video Digitizer Front-End
The AD9280ARSRL's 32 MSPS sampling rate is well-matched to digitizing standard-definition analog video streams (e.g., composite NTSC/PAL at 14.3 MSPS color subcarrier rates with margin). The 8-bit resolution captures broadcast-grade video with sufficient dynamic range for consumer DVD recording and video capture cards. The single +5 V supply and 95 mW dissipation keep the video digitizer PCB within thermal envelope without active cooling. The on-chip 300 MHz SHA eliminates the need for an external high-bandwidth buffer between the video amplifier and the ADC input. The internal voltage reference and three-state outputs simplify bus sharing when multiple video channels must be digitized into a shared FPGA or video processor.
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CCD/Camera Imaging Front-End
The AD9280ARSRL's 32 MSPS throughput and 8-bit resolution suit consumer digital still cameras and industrial CCD line-scan imaging at moderate frame rates. The on-chip sample-and-hold amplifier with 300 MHz input bandwidth captures the fast CCD output transients without external gating, while the integrated voltage reference holds the ADC full-scale stable across temperature variations in the imaging module. The single 2.7 V to 5.5 V supply enables direct connection to the camera module's main power rail, and the power-down sleep mode supports duty-cycled acquisition for battery-powered applications such as inspection drones or portable endoscopes. Three-state outputs permit parallel bus sharing across multiple sensor channels feeding a single DSP.
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Digital Oscilloscope Front-End
The AD9280ARSRL's 32 MSPS rate and 8-bit resolution enable entry-level digital storage oscilloscope (DSO) front-ends for bandwidths up to roughly 10 MHz, where single-shot bandwidth is the key spec. The pipelined architecture delivers deterministic latency that supports proper trigger positioning and equivalent-time sampling post-processing. The integrated SHA relaxes the analog input bandwidth requirement, allowing lower-cost front-end amplifiers to drive the ADC directly. The 28-pin SSOP package keeps the analog front-end compact and the 95 mW dissipation simplifies thermal design in handheld portable oscilloscope form factors. The out-of-range indicator simplifies trigger and detection logic for the FPGA downstream.
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IF Sampling in Communication Receivers
The AD9280ARSRL's 300 MHz input bandwidth allows direct IF sampling of intermediate-frequency signals in the 10-100 MHz range commonly used in narrowband communication receivers. The 32 MSPS throughput supports digital demodulation and DSP-based channel filtering, eliminating analog IF filter banks. The differential nonlinearity option and the ability to configure the analog input for differential operation improve common-mode rejection, which is essential for noisy RF environments. The wide 2.7 V to 5.5 V supply range supports integration with both portable radio battery packs and fixed 5 V industrial radio platforms. Three-state outputs permit bus sharing with control registers in the receiver baseband.
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Medical Ultrasound Imaging
The AD9280ARSRL is well-suited for entry-level portable medical ultrasound systems where 8-bit resolution and 32 MSPS sampling are sufficient for B-mode imaging of shallow structures. The integrated SHA and internal voltage reference minimize the analog front-end complexity required for each transducer channel, an important consideration when multi-element probe arrays are used. The power-down sleep mode between transmit/receive cycles reduces average system power, an essential factor for battery-powered point-of-care ultrasound devices. The wide supply range and 95 mW dissipation allow dense multi-channel PCB layouts within the probe head or handheld enclosure. The out-of-range indicator simplifies the beam-former logic for saturation detection.
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Industrial Process Control Data Acquisition
The AD9280ARSRL's wide 2.7 V to 5.5 V supply range and single-supply operation make it suitable for industrial process control and supervisory control and data acquisition (SCADA) modules that digitize analog sensor outputs. The 32 MSPS rate supports oversampling techniques that effectively improve measurement precision beyond the nominal 8-bit resolution. The integrated SHA and voltage reference eliminate external analog components, simplifying factory calibration procedures and reducing long-term drift. The 28-pin SSOP package and 95 mW dissipation suit DIN-rail-mounted industrial controllers where thermal density is a concern. The three-state outputs and power-down mode align with battery-backed industrial data loggers.
추천
추천 제품 요약
엔지니어링 참조 데이터: AD9280ARSRL — 비교, 설계 지침 및 규정 준수 정보.
선택 가이드
대체품과의 비교
| 파라미터 | 이 제품 | AD9280ARSZ | AD9280ARSZRL | AD9280ARS | AD9280ARSR | AD876-8ARSRL |
|---|---|---|---|---|---|---|
| Package | 28-SSOP | 28-SSOP - same | 28-SSOP - same | 28-SSOP - same | 28-SSOP - same | 28-SSOP - same |
| Brand | Analog Devices | Analog Devices - same | Analog Devices - same | Analog Devices - same | Analog Devices - same | Analog Devices - same |
| Resolution | 8 bits | 8 bits | 8 bits | 8 bits | 8 bits | 8 bits |
| Sampling Rate | 32 MSPS | 32 MSPS | 32 MSPS | 32 MSPS | 32 MSPS | 20 MSPS (-37.5%) |
| Supply Voltage | 2.7 V to 5.5 V | 2.7 V to 5.5 V | 2.7 V to 5.5 V | 2.7 V to 5.5 V | 2.7 V to 5.5 V | 5 V only (no 3 V operation) |
| Power Dissipation | 95 mW at 3 V | 95 mW at 3 V | 95 mW at 3 V | 95 mW at 3 V | 95 mW at 3 V | Higher at 5 V supply |
| RoHS Compliance | Yes (RL suffix) | Yes (Z suffix) | Yes (Z + RL) | No (non-RoHS) | No (non-RoHS) | Varies by suffix |
| Shipping Carrier | Tape & Reel | Tube | Tape & Reel | Tube | Tape & Reel | Tape & Reel |
주요 차별점
- Wider supply voltage range than legacy AD876-8 (vs AD876-8ARSRL)
- Higher sampling rate than legacy AD876-8 (vs AD876-8ARSRL)
- Integrated SHA eliminates external sample-and-hold (vs Discrete ADC + external SHA designs)
설계 노트
Estimated: at 3 V supply the AD9280ARSRL draws ~31.7 mA from AVDD for a total power dissipation of 95 mW. Designers should bypass AVDD with a 0.1 uF ceramic capacitor placed within 5 mm of the supply pin plus a 10 uF tantalum bulk capacitor. The DRVDD pin (digital supply) can be tied to AVDD or driven separately to reduce digital switching noise coupling into the analog front-end.
Per the Analog Devices AD9280 datasheet Rev. E, the analog input traces should be routed as 50 ohm controlled-impedance differential pairs with the SHA input pins decoupled by 5 pF shunt capacitors to AVDD. The digital output bus traces should be kept short and routed on a separate layer with a solid ground plane beneath to avoid coupling switching transients into the analog inputs through the package substrate.
Do not exceed the 5.5 V absolute maximum supply rating, as the on-chip reference will be damaged. The three-state output mode requires external bus arbitration when multiple AD9280ARSRL devices share a data bus to avoid contention. When using the high-pass coupling configuration, the CML or DC-offset reference capacitor value directly sets the high-pass corner frequency and must be selected based on the lowest frequency of interest.
Estimated: at 32 MSPS the digital output switching transients produce ~4 ns rise/fall edges. To prevent digital switching noise from coupling back into the analog input, place the output series resistors (typically 22 ohm) close to the ADC output pins and route the digital traces over a continuous ground plane. The out-of-range indicator pin should be monitored by the downstream FPGA to flag input overload conditions before downstream saturation occurs.
규정 준수 정보
RoHS compliance confirmed for the RL suffix per DigiKey listing 621660. REACH, halogen-free status, and conflict-minerals compliance are not stated in the verified web data and marked as unknown.