ADC0803LCN - 8-Bit SAR ADC, 10kSPS, 20-DIP | Texas Instruments
부품 번호: ADC0803LCN ✗ 단종| 수량 | 단가 | 합계 |
|---|---|---|
| 1 | $6.8 | $6.80 |
| 10 | $6.12 | $61.20 |
| 100 | $5.45 | $545.00 |
| 500 | $4.91 | $2,455.00 |
| 1,000 | $4.37 | $4,370.00 |
ADC0803LCN 개요
What is an SAR ADC? A successive-approximation register (SAR) analog-to-digital converter resolves an analog input to N bits by comparing the input against an internal DAC and walking a binary search through the registers on each clock edge. SAR ADCs sit in the broader hierarchy: ADC -> data converter -> mixed-signal IC -> semiconductor. They trade the speed of flash ADCs and the channel density of delta-sigma ADCs for low power, moderate latency, and a simple parallel/serial digital interface, which is exactly why the ADC0803 family has remained in legacy microprocessor designs for decades.
Key feature highlights include 8-bit resolution with ±1 LSB linearity (the "LCN" grade), a built-in differential potentiometric 256R ladder, on-chip clock generator, and three-state outputs that interface directly to 8080/6800 control buses. Power consumption is typically below 10 mW, and a differential analog input lets the device reject small ground offsets in noisy industrial buses.
The internal architecture combines a chopper-stabilized comparator, a successive-approximation register, a switched-capacitor DAC formed by the 256R ladder, and a parallel output latch. The 256R topology provides inherent monotonicity without trimming and gives a stable reference ladder that does not require a precision external reference, simplifying the BOM versus discrete ADC designs.
Typical applications include legacy industrial process-control loops, panel-meter readouts, battery monitoring for handheld equipment, and any 8080/6800/Z80 microcomputer analog front end where a low-cost, easy-to-interface 8-bit converter is acceptable. The differential input is also useful for thermocouple or bridge-type sensor readouts where one terminal sits above ground.
When designing with the ADC0803LCN, treat VREF/2 as the analog mid-scale reference; use a 10 kHz external clock or the internal RC oscillator and add 10 nF + 100 nF decoupling close to the supply pins. The through-hole 20-DIP footprint makes this part easy to breadboard but limits mounting density compared to modern SMD ADC alternatives.
This page synthesizes current distributor availability, parametric drop-in alternatives, and practical layout guidance that goes beyond the raw datasheet to support both legacy maintenance and new 8-bit analog designs.
드롭인 대체품: ADC0803LCN — 동일 패키지, 핀 호환. PCB 재작업이 필요한 다른 패키지 부품은 제외됩니다.
이 시리즈의 변형
다음과 드롭인 호환되는 동일 시리즈 모델: ADC0803LCN (동일 폼 팩터 및 풋프린트) — 차이점: Operating Temperature, Mounting Type, Resolution, Digital Interface, Input Type.
빠른 비교 도구 — 나란히 비교할 대체 부품을 선택하십시오:
ADC0803LCN/NOPB
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
ADC0804LCN
✅ 드롭인✓ 재고 있음
$3.84 / 개
데이터시트 보기 →ADC0802LCN
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
ADC0803LCN 최대 정격 & 전기적 특성
| 분해능 | 8 bits |
| 샘플링 속도 | 10 kSPS |
| Number of Inputs | 1 (differential) |
| Architecture | SAR (Successive Approximation) |
| Input Type | Differential, single-ended capable |
| 공급 전압 | 4.5 V to 6.3 V (single supply) |
| Digital Interface | Parallel, 8080/6800-compatible with three-state outputs |
| 데이터 버스 폭 | 8 bits |
| Linearity (DNL/INL) | ±1 LSB (LCN grade) |
| Reference Type | Internal 256R ladder, external VREF/2 tap |
| 동작 온도 | -40 C to +85 C |
| 패키지 | 20-DIP (PDIP, 0.300 inch, 7.62 mm) |
| 실장 유형 | Through-Hole |
ADC0803LCN 핀 구성
| 핀 1 | /CS — Chip select (active low) |
| 핀 2 | /RD — Read strobe (active low) |
| 핀 3 | /WR — Write strobe / conversion start (active low) |
| 핀 4 | /INTR — End-of-conversion interrupt (active low, open-drain) |
| 핀 5 | VIN+ — Differential analog input, non-inverting |
| 핀 6 | VIN- — Differential analog input, inverting (or analog ground) |
| 핀 7 | VREF/2 — External reference ladder mid-scale tap |
| 핀 8 | AGND — Analog ground (return for ladder and analog pin) |
| 핀 9 | DGND — Digital ground |
| 핀 10 | DB0 — Data bit 0 (three-state output) |
| 핀 11 | DB1 — Data bit 1 (three-state output) |
| 핀 12 | DB2 — Data bit 2 (three-state output) |
| 핀 13 | DB3 — Data bit 3 (three-state output) |
| 핀 14 | DB4 — Data bit 4 (three-state output) |
| 핀 15 | DB5 — Data bit 5 (three-state output) |
| 핀 16 | DB6 — Data bit 6 (three-state output) |
| 핀 17 | DB7 — Data bit 7 (three-state output, MSB) |
| 핀 18 | CLKR — Internal clock RC terminal (resistor to VCC) |
| 핀 19 | CLKIN — External clock input (or capacitor to GND for internal RC) |
| 핀 20 | VCC — Positive supply, 4.5 V to 6.3 V |
일반적인 애플리케이션
ADC0803LCN 적합 용도: 7 애플리케이션s: Legacy Industrial Process-Control Loops, Panel Meter and Digital Readout Designs, Battery Voltage Monitoring (5V-tolerant packs), 8080 / Z80 Microcomputer Analog Front End, Sensor Signal Digitization (Thermocouple / Bridge Front Ends), Data Acquisition Plug-In Cards (ISA/PC-104 Legacy Buses), Educational / Hobby Microcontroller Add-On Boards.
Legacy Industrial Process-Control Loops
The ADC0803LCN suits 4-20 mA loop readback and slow analog telemetry for legacy PLC backplanes, where 8-bit resolution over a 0-5 V span is sufficient. The 10 kSPS throughput handles valve position feedback and temperature channel scans well below oversample limits, and the differential analog input (VIN+/VIN-) rejects ground offsets that exist on long analog cables. The 20-DIP package is friendly to wire-wrap and prototyping frames used by industrial maintenance engineers, and the internal 256R ladder removes the need for a precision external reference, simplifying loop calibration in field installations.
추천
Panel Meter and Digital Readout Designs
The ADC0803LCN converts panel-meter analog signals to a 3.5-digit readable value with its 8-bit resolution. Connecting the differential input across the meter's sense resistor and using the internal ladder reference as the ADC reference yields a low-BOM digital panel meter that runs from a single 5 V supply. The ADC0803LCN's parallel output drives 7-segment decoders directly and its low <10 mW power consumption keeps the meter designer's heatsinking budget small. The 8080-compatible /RD, /WR, /CS handshake is overkill in this role but harmless - many panel-meter designs simply tie /WR low and strobe /RD each conversion cycle.
추천
Battery Voltage Monitoring (5V-tolerant packs)
For handheld battery packs that hold at 5 V or below, the ADC0803LCN samples the cell voltage through a resistor divider and reports SoC as an 8-bit value to the host microcontroller. The 4.5 V to 6.3 V supply range covers a single Li-Ion cell's full charge curve, and the differential input ignores ground bounce caused by switching regulators in the same pack. Because conversions occur at 10 kSPS, the host can average many samples and produce a low-noise pack telemetry channel. Designers should disable the ADC between reads to keep its quiescent draw negligible on standby current budgets.
추천
8080 / Z80 Microcomputer Analog Front End
The ADC0803LCN was designed explicitly to drop into 8080, 8085, 6800, and Z80 systems, where memory-mapped /CS, /RD, and /WR signals latch conversion results onto the data bus. This makes the part a one-chip AFE for 8-bit SBCs, retro computing expansion boards, and educational kits: a single /WR strobe starts the conversion, /INTR flags completion, and the next /RD cycle clocks the eight-bit result onto DB0-DB7. No glue logic or external latch is required, which is why the part remains popular for hobby and university coursework on microprocessor peripherals.
추천
Sensor Signal Digitization (Thermocouple / Bridge Front Ends)
For thermocouple and bridge-style sensors, the ADC0803LCN's differential input accommodates sensors whose negative terminal is not at ground, which makes it easy to digitize a K-type thermocouple with a small cold-junction compensation circuit. The 8-bit resolution is sufficient for industrial temperature controllers and load-cell displays with a 1000-2000 count usable range. The internal ladder lets designers ratiometrically measure sensors whose excitation comes from VCC, eliminating drift. Add a small op-amp front end (e.g., OPA277) to bring low-level sensor signals into the 0-5 V ADC input range for full-scale use of the 8-bit codes.
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Data Acquisition Plug-In Cards (ISA/PC-104 Legacy Buses)
The ADC0803LCN pairs naturally with ISA-bus and PC-104 cards where an 8-bit data word directly maps to the PC's lower data byte, simplifying the card's bus interface logic. The three-state output latch removes contention on the host data bus and the /INTR pin can be routed directly to an IRQ line. Even at 10 kSPS, a single ADC0803LCN provides enough throughput for legacy vibration monitors, audio VU meters, and slow instrumentation. Designers should add a 74HC245 buffer for backplanes with longer cable stubs so the ADC's modest drive strength does not degrade bus signal integrity.
추천
Educational / Hobby Microcontroller Add-On Boards
Universities and makers still teach 8-bit ADC principles with the ADC0803LCN because its 20-DIP form factor is easy to breadboard and its datasheet contains clear timing diagrams. The minimal external parts count (one resistor, one clock capacitor, a few bypass caps) lets students focus on the SAR algorithm instead of analog plumbing. Conversion results appear directly on eight LEDs when paired with a resistor-ladder display driver, making the part an iconic training vehicle for digital-electronics and microprocessor-interfacing labs. Hobby projects use it for robot sensor boards, retro gaming add-ons, and stand-alone instrumentation toys.
추천
추천 제품 요약
엔지니어링 참조 데이터: ADC0803LCN — 비교, 설계 지침 및 규정 준수 정보.
선택 가이드
대체품과의 비교
| 파라미터 | 이 제품 | ADC0803LCN/NOPB | ADC0804LCN | ADC0802LCN |
|---|---|---|---|---|
| Package | 20-DIP (PDIP) | 20-DIP (PDIP) | 20-DIP (PDIP) | 20-DIP (PDIP) |
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments |
| Resolution | 8 bits | 8 bits | 8 bits | 8 bits |
| Sampling Rate | 10 kSPS | 10 kSPS | 10 kSPS | 10 kSPS |
| Linearity | ±1 LSB (LCN grade) | ±1 LSB (LCN grade) | ±1 LSB (looser grade) | ±1/2 LSB (tightest grade) |
| Supply Voltage | 4.5 V to 6.3 V (single) | 4.5 V to 6.3 V (single) | 4.5 V to 6.3 V (single) | 4.5 V to 6.3 V (single) |
| Differential Input | Yes (VIN+/VIN-) | Yes (VIN+/VIN-) | Yes (VIN+/VIN-) | Yes (VIN+/VIN-) |
| Digital Interface | Parallel, 8080/6800 with three-state | Parallel, 8080/6800 with three-state | Parallel, 8080/6800 with three-state | Parallel, 8080/6800 with three-state |
| Lead-Free Finish | Pb-bearing (original) | Yes (RoHS lead-free) | Pb-bearing (LCN grade) | Pb-bearing (LCN grade) |
주요 차별점
- ±1 LSB (vs ±1 LSB looser grade on ADC0804LCN) linearity in the same footprint (vs ADC0804LCN)
- Direct 8080/6800/Z80 bus interface without glue logic (vs Generic discrete ADC + latch)
- Internal 256R reference ladder eliminates external precision reference (vs External reference plus resistor divider on competitor ADCs)
설계 노트
Decouple VCC (pin 20) with a 100 nF ceramic capacitor placed within 5 mm of the pin, in parallel with a 10 uF tantalum or aluminum electrolytic capacitor to ground. Without proper decoupling, the internal 256R ladder reference can bounce by several millivolts during data-bus switching, which directly appears as conversion noise. TI's datasheet typical applications add a 10 ohm series resistor to VCC and a 100 uF reservoir capacitor for industrial backplanes with long supply leads.
Do not leave VREF/2 (pin 7) floating. The internal 256R ladder derives its midpoint from this pin; if left open, the ADC output will saturate at one rail and conversions will return all-zero or all-FF codes. Tie VREF/2 to a low-impedance voltage reference derived from VCC, or to VCC/2 through a precision resistor divider bypassed with 10 uF.
Keep analog (VIN+, VIN-, VREF/2, AGND) traces short and isolated from digital output bus (DB0-DB7, /CS, /RD, /WR, /INTR) crossings. Route AGND and DGND back to a single-point star ground at the ADC's pin 9 to avoid ground loops that couple the eight three-state output transitions back into the analog input. The PDIP package's long leads make it easy to accidentally create an antenna loop, so use a ground plane on the bottom layer.
Driving the three-state parallel outputs with another device will cause bus contention and can damage either driver. Always deassert /CS (pin 1) before another device uses DB0-DB7; better, route /CS to the decoded address line of the host bus so it goes high when the ADC is not selected. Leaving /INTR floating is acceptable because it is open-drain, but it must have a pull-up to VCC if the host relies on the interrupt output.
규정 준수 정보
The original ADC0803LCN (suffix LCN) is the tin-lead PDIP variant; the lead-free equivalent is ADC0803LCN/NOPB. Verified Web Data does not explicitly list RoHS/REACH compliance or halogen-free status; AEC-Q100 is not applicable because this is not an automotive-qualified part. Designers targeting RoHS should choose ADC0803LCN/NOPB explicitly.
