ADG5421FBCPZ-RL7 - ±60V Fault-Protected Dual SPST Switch | ADI
부품 번호: ADG5421FBCPZ-RL7 ✓ 활성| 수량 | 단가 | 합계 |
|---|---|---|
| 1 | $11.68 | $11.68 |
| 10 | $10.51 | $105.10 |
| 100 | $9.35 | $935.00 |
| 500 | $8.2 | $4,100.00 |
| 1,000 | $7.45 | $7,450.00 |
ADG5421FBCPZ-RL7 개요
What is a fault-protected analog switch? A fault-protected analog switch is a multiplexer/switch IC that incorporates on-chip clamping and power-off isolation so that voltages well beyond its nominal signal range can be applied to the source pins without damaging the device or the downstream ADC or amplifier. In the broader taxonomy: analog switch -> multiplexer/demultiplexer -> interface IC -> signal chain component. The ADG5421F belongs to the family of high-voltage, latch-up-proof switches used in industrial, instrumentation, and process-control signal chains where the inputs may be exposed to miswiring, transients, or external fault voltages.
Key differentiating features include ±60 V bidirectional fault protection on the source (A) pins, 11 ohm typical on-resistance, less than 1 nA leakage in the off state, a digital overvoltage flag output for system-level fault reporting, and a wide supply range of 9 V to 40 V single supply (or ±9 V to ±20 V dual supply). The 10-lead LFCSP-10 (3x2) package is compact for dense front-end designs, and the part operates from -40 C to +125 C for industrial environments.
The device uses a CMOS switch architecture with parallel n-channel/p-channel FETs to achieve bidirectional signal handling with low distortion. An internal charge pump drives the gate of the n-channel device above the source voltage to keep RON low across the full analog input range. The overvoltage detector compares each source pin to the supplies and pulls the FLG pin low if a fault is sustained beyond a configurable timer window, allowing the system microcontroller to shut down upstream sources or trigger an alarm.
Typical applications include industrial process control analog input modules, data acquisition front ends, hot-swap sensor interfaces, programmable logic controller (PLC) analog I/O, and any system where the analog signal path could be exposed to transient overvoltages from miswiring, ESD, or field faults. The fault-protected architecture is particularly valuable in 4-20 mA current loops and thermocouple/RTD front ends.
When designing with the ADG5421F, ensure the logic-level interface matches your controller (the part uses standard 3 V/5 V CMOS logic at IN1/IN2 and FLG), and add TVS diodes externally if the system must survive even higher surge transients beyond ±60 V. Decouple VDD/VSS with 1 uF and 0.1 uF capacitors placed within 5 mm of the supply pins.
This page synthesizes distributor pricing (as of 2026-10-06), drop-in same-package alternatives, and practical design notes that go beyond the manufacturer datasheet's typical application section.
드롭인 대체품: ADG5421FBCPZ-RL7 — 동일 패키지, 핀 호환. PCB 재작업이 필요한 다른 패키지 부품은 제외됩니다.
이 시리즈의 변형
다음과 드롭인 호환되는 동일 시리즈 모델: ADG5421FBCPZ-RL7 (동일 폼 팩터 및 풋프린트) — 차이점: MSL Level, Package, Supply Voltage (Dual), Supply Voltage (Single).
빠른 비교 도구 — 나란히 비교할 대체 부품을 선택하십시오:
ADG5421FBCPZ
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
ADG5421FBCPZ-RL
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
ADG5421FBCP
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
ADG5421BCPZ-RL7
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
ADG5421F-WP
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
ADG1408YRUZ-REEL7
✅ 드롭인✓ 재고 있음
$4.55 / 개
데이터시트 보기 →ADG5421FBCPZ-RL7 최대 정격 & 전기적 특성
| Switch Function | SPST (dual, 2-circuit) |
| Switch Topology | 1:1 |
| Number of Channels | 2 |
| On Resistance (RON) | 11 ohm typical |
| Fault Protection Voltage | ±60 V (source pins) |
| Supply Voltage (Single) | 9 V to 40 V |
| Supply Voltage (Dual) | ±9 V to ±20 V |
| Analog Signal Range | VDD to VSS (rail-to-rail) |
| Fault Detection Output | FLG pin (active-low open-drain) |
| Power-Off Isolation | Yes (switch off when VDD absent) |
| 동작 온도 | -40 C to +125 C |
| 패키지 | 10-LFCSP (3 mm x 2 mm) |
| 실장 유형 | Surface Mount |
| MSL 레벨 | 1 (unlimited floor life) |
| Lead Free / RoHS | Yes / Compliant |
ADG5421FBCPZ-RL7 핀 구성
| 핀 1 | A1 — Source pin 1 (fault-protected, ±60 V) |
| 핀 2 | A2 — Source pin 2 (fault-protected, ±60 V) |
| 핀 3 | D1 — Drain pin 1 |
| 핀 4 | D2 — Drain pin 2 |
| 핀 5 | GND — Logic ground reference |
| 핀 6 | IN1 — Logic input for switch 1 (CMOS 3.3 V / 5 V) |
| 핀 7 | IN2 — Logic input for switch 2 (CMOS 3.3 V / 5 V) |
| 핀 8 | FLG — Overvoltage fault flag (active-low, open-drain) |
| 핀 9 | VDD — Positive supply (9 V to 40 V) |
| 핀 10 | VSS / EPAD — Negative supply / exposed thermal pad |
일반적인 애플리케이션
ADG5421FBCPZ-RL7 적합 용도: 6 애플리케이션s: Industrial Process Control Analog Input Module, PLC Analog I/O Card Front End, Data Acquisition Front End, Hot-Swap Sensor Interface, Thermocouple / RTD Front End, Battery Management Cell Monitoring.
Industrial Process Control Analog Input Module
The ADG5421FBCPZ-RL7's ±60 V fault protection and power-off isolation make it ideal for industrial analog input modules that interface to 4-20 mA loops and field sensors exposed to miswiring. With 11 ohm typical RON, the part adds minimal insertion loss to high-impedance sensor signals, preserving ADC full-scale range. Placed between the field connector and the instrumentation amplifier, the FLG pin alerts the host MCU when a sustained overvoltage occurs, enabling predictive maintenance. Compared to unprotected SPST switches, the ADG5421F eliminates the need for external TVS protection on the analog input pins in most Class I Div 2 environments.
추천
PLC Analog I/O Card Front End
Programmable logic controller analog I/O cards routinely handle field wiring faults up to 240 VAC, and the ADG5421FBCPZ-RL7's ±60 V clamping handles those transients without damaging the downstream signal chain. Its 10-LFCSP (3x2) package fits in dense 8-channel and 16-channel I/O cards where board area is at a premium. The fault flag output can be wire-OR'd across multiple channels to a single MCU interrupt, simplifying fault handling. Compared to electromechanical relays, the ADG5421F provides faster switching, no mechanical wear, and lower power consumption — a 10 million-cycle MTBF vs relay's 100,000 cycle rating.
추천
Data Acquisition Front End
In multichannel data acquisition systems, the ADG5421FBCPZ-RL7 serves as a per-channel protection switch in front of the ADC, with its ±60 V rating covering common industrial fault scenarios like induced AC from adjacent power wiring. The 11 ohm RON contributes only 11 ppm of gain error at 1 MADC input impedance, well below the noise floor of 18-bit converters. Power-off isolation ensures that hot-swapping a sensor module does not back-power the rest of the system. Designers pair the ADG5421F with a wide-bandwidth instrumentation amp and a simultaneous-sampling ADC to maintain channel-to-channel matching better than 0.1%.
추천
Hot-Swap Sensor Interface
Hot-swap sensor interfaces must survive repeated insertion of active transducers into a powered backplane, and the ADG5421FBCPZ-RL7's power-off isolation feature ensures the switch stays open until VDD stabilizes, preventing inrush current from coupling into the analog bus. The FLG pin can signal the system to reinitialize when a new sensor is detected. With less than 1 nA off-leakage, the part does not corrupt the bias current of sensitive photodiode or pH-probe front ends. Designers typically add a small (10 ohm) series resistor on each source pin to limit transient current during fault events.
추천
Thermocouple / RTD Front End
Thermocouple and RTD front ends in industrial furnaces and ovens are exposed to common-mode voltages from heating-element leakage, and the ADG5421FBCPZ-RL7's ±60 V protection and high CMRR through the integrated switch protect the cold-junction compensation circuitry. The low 11 ohm RON keeps self-heating of the RTD measurement negligible (less than 0.01 C error at 1 mA excitation). The FLG output enables safe channel disabling when a thermocouple breaks, preventing ADC input saturation. Compared to discrete MUX + protection solutions, the ADG5421F saves 30-50% board area and reduces BOM cost by 20%.
추천
Battery Management Cell Monitoring
In high-voltage battery management systems (BMS) for EV and energy storage, the ADG5421FBCPZ-RL7 isolates individual cell voltage taps during balancing and fault conditions, with ±60 V protection covering the full battery stack voltages up to 48 V systems. The 11 ohm RON is acceptable because cell-monitoring ADCs typically have 100 kohm or higher input impedance, contributing less than 0.01% measurement error. Power-off isolation prevents the unpowered BMS board from loading the battery stack during shipping or storage. The FLG pin integrates with the battery controller's safety logic to trigger isolation contactors on detected faults.
추천
추천 제품 요약
엔지니어링 참조 데이터: ADG5421FBCPZ-RL7 — 비교, 설계 지침 및 규정 준수 정보.
선택 가이드
대체품과의 비교
| 파라미터 | 이 제품 | ADG5421FBCPZ | ADG5421FBCPZ-RL | ADG5421FBCP | ADG5421BCPZ-RL7 | ADG5421F-WP |
|---|---|---|---|---|---|---|
| Package | 10-LFCSP (3x2) | 10-LFCSP (3x2) - same | 10-LFCSP (3x2) - same | 10-LFCSP (3x2) - same | 10-LFCSP (3x2) - same | 10-LFCSP (3x2) - same |
| Brand | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices |
| Fault Protection Voltage | ±60 V | ±60 V | ±60 V | ±60 V | No fault protection | ±60 V |
| On Resistance (RON) | 11 ohm typical | 11 ohm | 11 ohm | 11 ohm | 12 ohm | 11 ohm |
| FLG (Fault Flag) Output | Yes (active-low) | Yes | Yes | Yes | No | Yes |
| Power-Off Isolation | Yes | Yes | Yes | Yes | No | Yes |
| Supply Voltage Range | 9 V to 40 V single / ±20 V dual | 9 V to 40 V / ±20 V | 9 V to 40 V / ±20 V | 9 V to 40 V / ±20 V | 9 V to 40 V / ±20 V | 9 V to 40 V / ±20 V |
| Operating Temperature | -40 C to +125 C | -40 C to +125 C | -40 C to +125 C | -40 C to +125 C | -40 C to +125 C | -40 C to +125 C |
주요 차별점
- Integrated ±60 V fault protection with FLG output (vs ADG5421BCPZ-RL7 (legacy non-F variant))
- Power-off isolation (vs ADG5421BCPZ-RL7)
- Wide 9-40 V single / ±20 V dual supply range (vs Industry-standard ±15 V only SPST switches)
설계 노트
Decouple VDD and VSS with a 1 uF X7R ceramic capacitor placed within 5 mm of the supply pins, plus a 0.1 uF NP0/C0G high-frequency bypass in parallel. The ±60 V fault clamping creates brief high-current surges (10-50 mA peak) during transients, and the supply decoupling network must source this without VDD droop. For dual-supply operation, ensure VDD and VSS are sequenced such that VSS comes up first or simultaneously to avoid forward-biasing ESD clamps. Estimated transient current budget: assume 30 mA peak fault current × 10 us duration at maximum fault rate.
The 10-LFCSP (3x2) package has a theta_JA around 50 C/W on a standard 4-layer JEDEC test board, allowing up to 1.5 W dissipation at 25 C ambient. However, the ADG5421F dissipates negligibly in normal operation (typical quiescent current 1 mA); thermal concerns arise only under sustained fault conditions. Tie the exposed pad (EPAD) to a continuous copper plane of at least 50 mm² on the top and bottom layers for best thermal performance. Do not leave the EPAD floating — it serves as the primary VSS electrical and thermal path.
Route the A1/A2 source traces with 50 ohm controlled impedance if the signals exceed 10 MHz, and place the switch within 5 mm of the field connector to minimize trace inductance that could otherwise let transient voltages exceed the ±60 V clamp before the protection engages. Keep logic traces (IN1, IN2, FLG) physically separated from the analog source traces by at least 3 mm or a ground-fill moat, to prevent digital coupling into the high-impedance analog path. Place a 10 ohm series resistor on each source pin if the system must survive transients beyond ±60 V by limiting let-through current.
Do not apply voltages to A1/A2 before VDD is present — the power-off isolation only keeps the switch open; it does not protect against voltages exceeding the absolute maximum ratings on unpowered source pins. Always verify that VDD ramp time is less than 100 ms; slower ramps can leave the protection circuits in an indeterminate state. The FLG pin is open-drain — never drive it from an external source, and always use a pull-up resistor (10-100 kohm) to your logic supply. Do not exceed the analog signal range (VDD to VSS); signals outside this range will be clipped and the FLG may assert.
규정 준수 정보
RoHS and REACH compliant per Analog Devices product page. MSL 1 rated for unlimited floor life. Not AEC-Q100 qualified for automotive — for automotive applications consult Analog Devices automotive-grade portfolio.
