ADS6123IRHBR - 12-Bit 65MSPS Low-Power ADC | Texas Instruments
부품 번호: ADS6123IRHBR ✓ 활성| 수량 | 단가 | 합계 |
|---|---|---|
| 1 | $14.5 | $14.50 |
| 10 | $13.2 | $132.00 |
| 100 | $11.85 | $1,185.00 |
| 500 | $10.6 | $5,300.00 |
| 1,000 | $9.4 | $9,400.00 |
ADS6123IRHBR 개요
An ADC (analog-to-digital converter) is a mixed-signal integrated circuit that samples continuous analog waveforms and produces discrete digital codes at a specified sample rate. ADCs sit between the analog front-end (amplifiers, filters) and the digital processing block (FPGA, ASIC, microcontroller), translating real-world signals (IF, baseband, video, sensor outputs) into a digital representation that downstream logic can analyze. The ADS6123 belongs to the pipelined ADC class, which uses a multi-stage architecture to balance high sample rates with low power consumption and small die area.
Key specifications of the ADS6123IRHBR include 12-bit resolution, 65 MSPS maximum sample rate (the slowest member of the ADS612x family, which extends to 125 MSPS for ADS6125), 1 input channel, and integrated analog input buffer (the ADS612x family supports buffered or unbuffered input modes). It operates from a single 3.3 V analog supply and a separate 1.8 V digital supply, providing typical SNR around 70 dBFS and SFDR above 80 dBc at low input frequencies.
The pipelined architecture uses multiple cascaded low-resolution stages to convert a single sample across several clock cycles, achieving a high throughput while consuming moderate power per conversion. The device supports internal reference voltage generation, eliminating the need for external reference components and reducing BOM cost in space-constrained designs.
Typical applications include wireless communication receivers, portable ultrasound imaging, digital oscilloscopes, IF digitization, and CCD/camera signal chains. The 65 MSPS sample rate is well suited for digitizing intermediate-frequency signals in narrow-band radios and for low-frequency medical imaging front-ends. Designers benefit from selectable output interfaces when the same board design must serve different FPGA platforms.
When designing with the ADS6123IRHBR, ensure clean analog and digital supply decoupling using 0.1 µF ceramic capacitors placed within 5 mm of each supply pin, and provide a solid ground plane under the exposed thermal pad for optimal thermal and EMI performance. The DDR LVDS output mode may require 100 Ω termination at the FPGA side.
This page synthesizes distributor pricing, drop-in pin-compatible alternatives within the ADS612x family, and practical design notes not found in the manufacturer datasheet alone.
드롭인 대체품: ADS6123IRHBR — 동일 패키지, 핀 호환. PCB 재작업이 필요한 다른 패키지 부품은 제외됩니다.
이 시리즈의 변형
다음과 드롭인 호환되는 동일 시리즈 모델: ADS6123IRHBR (동일 폼 팩터 및 풋프린트) — 차이점: Package, RoHS Status, Analog Supply Voltage, Output Interface, Digital Supply Voltage.
빠른 비교 도구 — 나란히 비교할 대체 부품을 선택하십시오:
ADS6123IRHBT
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
ADS6122IRHBR
✅ 드롭인✓ 재고 있음
$12.5 / 개
데이터시트 보기 →ADS6124IRHBR
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
ADS6125IRHBR
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
ADS6142IRHBR
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
ADS6123IRHBR 최대 정격 & 전기적 특성
| 분해능 | 12 bits |
| Number of Input Channels | 1 |
| Sample Rate (Max) | 65 MSPS |
| Architecture | Pipelined |
| Input Type | Differential |
| Output Interface | Parallel CMOS or DDR LVDS (selectable) |
| Analog Supply Voltage | 3.3 V (nominal) |
| Digital Supply Voltage | 1.8 V (nominal) |
| 패키지 | 32-VQFN (5x5 mm) with exposed pad |
| 실장 유형 | Surface Mount |
| 동작 온도 범위 | -40 °C to +85 °C |
| Internal Reference | Yes (per ADS612x family) |
| Input Buffer | Selectable buffered / unbuffered (per family) |
| RoHS 상태 | Pb-Free (RoHS compliant) per TI datasheet |
| Family Series | ADS612x (ADS6122 / ADS6123 / ADS6124 / ADS6125) |
ADS6123IRHBR 핀 구성
| 핀 1 | INP — Differential analog input positive (per ADS612x datasheet family) |
| 핀 2 | INN — Differential analog input negative (per ADS612x datasheet family) |
| 핀 3 | VCM — Common-mode voltage output (per ADS612x datasheet family) |
| 핀 4 | AVDD — Analog 3.3 V supply |
| 핀 5 | AGND — Analog ground |
| 핀 6 | REFT — Reference decoupling top |
| 핀 7 | REFB — Reference decoupling bottom |
| 핀 8 | AVDD — Analog 3.3 V supply |
| 핀 9 | AGND — Analog ground |
| 핀 10 | SEN — Input-buffer enable / sense (family-dependent) |
| 핀 11 | SCLK — Serial programming clock (family register access) |
| 핀 12 | SDATA — Serial programming data |
| 핀 13 | RESET — Hardware reset |
| 핀 14 | CLK — Sampling clock input |
| 핀 15 | CLKB — Complementary sampling clock input |
| 핀 16 | DVDD — Digital 1.8 V supply |
| 핀 17 | DGND — Digital ground |
| 핀 18 | D0 — Data output bit 0 |
| 핀 19 | D1 — Data output bit 1 |
| 핀 20 | D2 — Data output bit 2 |
| 핀 21 | D3 — Data output bit 3 |
| 핀 22 | D4 — Data output bit 4 |
| 핀 23 | D5 — Data output bit 5 |
| 핀 24 | D6 — Data output bit 6 |
| 핀 25 | D7 — Data output bit 7 |
| 핀 26 | D8 — Data output bit 8 |
| 핀 27 | D9 — Data output bit 9 |
| 핀 28 | D10 — Data output bit 10 |
| 핀 29 | D11 — Data output bit 11 |
| 핀 30 | OUTMODE — Output interface select (CMOS / DDR LVDS) |
| 핀 31 | DGND — Digital ground |
| 핀 32 | DRVDD — Digital output driver supply (1.8 V) |
일반적인 애플리케이션
ADS6123IRHBR 적합 용도: 6 애플리케이션s: Wireless IF Digitization, Portable Ultrasound Imaging, Digital Oscilloscope / Data Acquisition, CCD / Camera Signal Chain, Communications Test Equipment, Industrial Process Control / Sensor Digitization.
Wireless IF Digitization
The ADS6123IRHBR's 65 MSPS sample rate is well matched to narrow-band intermediate-frequency (IF) digitization in wireless receivers, where the IF sits between the mixer and the baseband DSP. Placing the part after the IF SAW filter and a low-noise driver amplifier, designers benefit from the selectable DDR LVDS output for clean transfer to an FPGA demodulator at >400 Mbps, while the integrated input buffer absorbs the upstream filter's reactive impedance. Compared with a 14-bit/125 MSPS ADS6145, the ADS6123 saves power and cost when 12-bit/65 MSPS bandwidth is sufficient.
추천
Portable Ultrasound Imaging
In portable ultrasound front-ends, the ADS6123IRHBR digitizes multi-channel transducer arrays at low to moderate sample rates, balancing power dissipation with adequate SNR for image reconstruction. Each channel uses one ADS6123 (or its lower-power ADS6122 at 40 MSPS) running from a 3.3 V analog rail, with the parallel CMOS output feeding a portable FPGA for beam steering. The 32-VQFN footprint simplifies dense multi-channel board layouts; the ADS6123's selectable buffered input mode helps isolate the transducer's high-impedance source from the ADC sampling network.
추천
Digital Oscilloscope / Data Acquisition
Low-cost two-channel benchtop oscilloscopes and modular data-acquisition cards use the ADS6123IRHBR to digitize wideband input signals. At 65 MSPS, the part comfortably samples a 30 MHz analog front-end satisfying typical 25 MHz scope bandwidth targets. The DDR LVDS output mode pairs naturally with low-cost FPGAs such as the XC6SLX16, while designers targeting 14-bit vertical resolution can step up to the ADS6142IRHBR in the same package. This is a high-value upgrade path versus 10-bit ADCs used in entry-level scopes.
추천
CCD / Camera Signal Chain
Industrial and machine-vision cameras use the ADS6123IRHBR to digitize CCD output signals after correlated double sampling. The 12-bit resolution captures 4096 gray levels - adequate for monochrome inspection cameras - while the 65 MSPS sample rate supports pixel clock rates up to 65 MHz for high-line-rate line-scan cameras. The integrated input buffer absorbs the CCD output amplifier's switching transients, reducing the need for an external high-speed buffer. The CMOS output mode simplifies interface to low-cost image processors such as the DM385.
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Communications Test Equipment
Spectrum analyzers, signal generators, and communications test platforms use the ADS6123IRHBR to capture IF or baseband signals for analysis. The combination of 12-bit granularity, 65 MSPS, and selectable DDR LVDS outputs enables capture of modulated signals (QAM, OFDM, FM) with adequate spurious-free dynamic range for vector-signal analysis. The same PCB footprint as the ADS6125 (125 MSPS) lets designers reuse the layout for higher-bandwidth models without board rework, lowering development cost.
추천
Industrial Process Control / Sensor Digitization
In industrial 4-20 mA loop digitization, vibration monitoring, and multi-channel sensor acquisition systems, the ADS6123IRHBR provides low-power 12-bit conversion at 65 MSPS for oversampled measurements. Industrial environments demand the part's industrial -40 °C to +85 °C temperature range and RoHS compliance for global deployment. A typical architecture pairs one ADS6123 per sensor channel with an ARM Cortex-M4 microcontroller for data aggregation, leveraging the CMOS output for simple parallel capture.
추천
추천 제품 요약
엔지니어링 참조 데이터: ADS6123IRHBR — 비교, 설계 지침 및 규정 준수 정보.
선택 가이드
대체품과의 비교
| 파라미터 | 이 제품 | ADS6123IRHBT | ADS6122IRHBR | ADS6124IRHBR | ADS6125IRHBR | ADS6142IRHBR |
|---|---|---|---|---|---|---|
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments |
| Package | VQFN-32 (RHB) 5x5 mm | VQFN-32 (RHB) 5x5 mm - same | VQFN-32 (RHB) 5x5 mm - same | VQFN-32 (RHB) 5x5 mm - same | VQFN-32 (RHB) 5x5 mm - same | VQFN-32 (RHB) 5x5 mm - same |
| Resolution | 12 bits | 12 bits | 12 bits | 12 bits | 12 bits | 14 bits |
| Max Sample Rate | 65 MSPS | 65 MSPS | 40 MSPS (-38%) | 105 MSPS (+62%) | 125 MSPS (+92%) | 65 MSPS |
| Output Interface | CMOS / DDR LVDS | CMOS / DDR LVDS | CMOS / DDR LVDS | CMOS / DDR LVDS | CMOS / DDR LVDS | CMOS / DDR LVDS |
| Analog Supply | 3.3 V | 3.3 V | 3.3 V | 3.3 V | 3.3 V | 3.3 V |
| Digital Supply | 1.8 V | 1.8 V | 1.8 V | 1.8 V | 1.8 V | 1.8 V |
| Number of Input Channels | 1 | 1 | 1 | 1 | 1 | 1 |
| Operating Temperature Range | -40 °C to +85 °C | -40 °C to +85 °C | -40 °C to +85 °C | -40 °C to +85 °C | -40 °C to +85 °C | -40 °C to +85 °C |
| RoHS Status | Pb-Free (RoHS compliant) | Pb-Free (RoHS compliant) | Pb-Free (RoHS compliant) | Pb-Free (RoHS compliant) | Pb-Free (RoHS compliant) | Pb-Free (RoHS compliant) |
주요 차별점
- Pin-compatible family member with selectable sample rate (vs ADS6125IRHBR)
- Versatile output interface on one part (vs ADS6122IRHBR)
- Integrated input buffer option (vs ADS6142IRHBR)
설계 노트
Place 0.1 µF ceramic decoupling capacitors as close as possible (within 5 mm) to every AVDD and DVDD pin of the ADS6123IRHBR. Use a solid ground plane directly under the exposed thermal pad and stitch vias around the pad to the inner ground layer for low-impedance return paths. Per the TI ADS612x datasheet, keeping analog and digital grounds separated at the IC and joined only at a single point near the regulator reduces noise coupling into the analog front-end.
When using the DDR LVDS output mode, route the differential data pairs (D0-D11 + CLK/CLKB) with 100 Ω differential impedance, length-matched within 1 mm, and terminated with 100 Ω at the FPGA receiver. For CMOS output mode, place 22 Ω series-termination resistors close to the ADC data pins to dampen reflections into the 1.8 V digital supply. Keep the analog input traces short and guarded by ground traces to minimize sampling kick-back glitches.
Do not exceed the 3.3 V analog supply tolerance - the ADS6123IRHBR is not 5 V tolerant on AVDD. Ensure the common-mode voltage (VCM) pin is properly bypassed with a 0.1 µF capacitor; failure to do so degrades SNR by 3-5 dB. When switching between CMOS and DDR LVDS modes, reset the device after toggling the OUTMODE pin. Finally, avoid long parallel runs between the analog input and digital outputs to prevent digital switching noise from coupling back into the input.
규정 준수 정보
Pb-Free / RoHS compliant per TI ADS612x datasheet. Industrial -40 °C to +85 °C temperature grade. AEC-Q100 not applicable for this industrial-grade ADC.
