ADS821 - 10-Bit 40MSPS ADC Internal Ref | TI
부품 번호: ADS821 ✓ 활성| 수량 | 단가 | 합계 |
|---|---|---|
| 1 | $18.5 | $18.50 |
| 10 | $16.65 | $166.50 |
| 100 | $14.8 | $1,480.00 |
| 500 | $13.3 | $6,650.00 |
| 1,000 | $11.95 | $11,950.00 |
ADS821 개요
A pipelined ADC is an analog-to-digital converter that uses a cascade of low-resolution stages to achieve high sampling rates while maintaining reasonable power consumption. In the ADC hierarchy, the ADS821 is a high-speed pipelined converter within the broader category of data converters, which sit between analog signals and digital signal processors in a signal chain. Pipelined ADCs are used where both high speed and moderate resolution (10 to 14 bits) are required.
The ADS821 provides no missing codes, a high SNR of 58 dB, and power dissipation of only 380 mW at 40 MSPS, which is low for a 10-bit 40MHz CMOS converter. The integrated track-and-hold removes the need for an external sample-and-hold amplifier, and the internal reference reduces external component count. The power-down feature reduces system power during idle periods.
Architecturally, the device uses a pipelined conversion architecture optimized for conversion rates up to 40 MSPS. Differential input capability improves common-mode rejection and reduces even-order harmonic distortion compared to single-ended drive. Digital outputs drive standard CMOS logic, simplifying interfacing to FPGAs, DSPs, or microcontrollers in single-supply +5V systems.
Typical applications include medical ultrasound signal digitizing, video and CCD digitizing, digital oscilloscope front-ends, industrial data-acquisition boards, and communications IF sampling. The combination of internal reference, internal track-and-hold, and 40MSPS throughput makes the ADS821 an efficient building block for high-speed acquisition channels.
When designing with the ADS821, use a low-impedance analog source or high-speed op-amp driver to ensure differential input settling within one sample period. Decouple all supply pins and keep the analog input path short and shielded for best SNR.
드롭인 대체품: ADS821 — 동일 패키지, 핀 호환. PCB 재작업이 필요한 다른 패키지 부품은 제외됩니다.
빠른 비교 도구 — 나란히 비교할 대체 부품을 선택하십시오:
ADS825U
✅ 드롭인 ⚠️ 사양 미검증📋 참조 대체품 (카탈로그에 없음)
ADS826U
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
TLC5510I
✅ 드롭인 ⚠️ 사양 미검증📋 참조 대체품 (카탈로그에 없음)
AD9200ARS
✅ 드롭인 ⚠️ 사양 미검증📋 참조 대체품 (카탈로그에 없음)
ADS821UG4
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
ADS821 최대 정격 & 전기적 특성
| 분해능 | 10 bit |
| 샘플링 속도 | 40 MSPS |
| Architecture | Pipelined |
| Number of Inputs | 1 |
| Input Type | Differential or Single-Ended |
| 공급 전압 | +5 V single supply |
| Power Dissipation | 380 mW |
| SNR | 58 dB |
| Reference | Internal |
| Track-and-Hold | Internal |
| Power Down | Yes |
| Missing Codes | No missing codes |
| 패키지 | SO-28 / SSOP-28 |
| 실장 유형 | Surface Mount |
| Process Technology | Small geometry CMOS |
| Output Interface | Parallel CMOS |
ADS821 핀 구성
| 핀 1 | IN — Analog input (+) / single-ended input |
| 핀 2 | COM — Common-mode / reference bypass |
| 핀 3 | REF — Internal reference output |
| 핀 4 | REFT — Reference top sense |
| 핀 5 | REFB — Reference bottom sense |
| 핀 6 | AVDD — Analog supply +5V |
| 핀 7 | AGND — Analog ground |
| 핀 8 | DVDD — Digital supply +5V |
| 핀 9 | DGND — Digital ground |
| 핀 10 | CLK — Sampling clock input |
| 핀 11 | PD — Power-down control |
| 핀 12 | OE — Output enable |
| 핀 14-23 | D0-D9 — 10-bit parallel CMOS data output |
| 핀 28 | OVR — Overrange flag output |
일반적인 애플리케이션
ADS821 적합 용도: 6 애플리케이션s: Medical Ultrasound Digitizing, Digital Storage Oscilloscope Front-End, Video and CCD Digitizing, Industrial Data Acquisition, Communications IF Sampling, Test and Measurement Instrumentation.
Medical Ultrasound Digitizing
The ADS821 fits ultrasound beamformer receive chains where 40 MSPS sampling covers the transducer IF content and 58 dB SNR preserves gray-scale image quality. Its internal track-and-hold removes an external S/H amplifier per channel, and 380 mW per converter keeps multi-channel probe front-ends inside typical power budgets. Designers pair it with low-noise VGA outputs driven differentially to exploit common-mode rejection and reduce even-order distortion in the image path.
추천
Digital Storage Oscilloscope Front-End
Entry-level DSO channels use the ADS821 for 40 MSPS waveform capture. The pipelined architecture delivers one conversion per clock cycle, and no missing codes guarantees monotonic waveform display. The single +5V supply simplifies instrument power rails, while the power-down mode conserves power in multi-channel scopes during idle time. An OPA698 or similar high-speed op-amp buffers the front-end attenuator into the differential input for settled sampling within the 25 ns period.
추천
Video and CCD Digitizing
The ADS821 digitizes composite video and CCD sensor outputs where pixel rates fall within 40 MSPS. Its 58 dB SNR supports broadcast-grade luminance accuracy, and single-ended input mode directly accepts AC-coupled video via clamp circuitry. The internal reference removes external reference ICs, reducing BOM cost per channel in multi-channel video capture cards; differential mode suits differential-output CCD readout paths with improved common-mode noise rejection.
추천
Industrial Data Acquisition
Industrial acquisition boards digitize sensor and IF signals with the ADS821 where 10-bit resolution and 40 MSPS suffice. The parallel CMOS output interfaces directly to FPGAs or DSPs, and the +5V rail matches legacy industrial logic. Power-down mode cuts consumption between bursts in triggered acquisition systems. Solid grounding and supply decoupling preserve the 58 dB SNR in electrically noisy factory environments near drives and switching converters.
추천
Communications IF Sampling
Receiver IF chains sample intermediate frequencies directly with the ADS821 at up to 40 MSPS. Differential input operation suppresses common-mode LO feedthrough and lowers even-order harmonics, improving spurious-free dynamic range before digital down-conversion. At 380 mW, the converter suits compact radio designs where per-channel power matters, and the internal reference removes a dedicated reference IC from the receive card layout.
추천
Test and Measurement Instrumentation
Bench instruments, spectrum-scan receivers, and automated test channels use the ADS821 as a compact 10-bit digitizer. The complete converter (internal reference plus track-and-hold) shortens design time, while 40 MSPS supports fast transient capture. The power-down pin enables duty-cycled measurements that extend battery life in portable instruments, and the SO-28 through-hole-friendly footprint eases prototyping and rework on test fixtures.
추천
추천 제품 요약
엔지니어링 참조 데이터: ADS821 — 비교, 설계 지침 및 규정 준수 정보.
선택 가이드
대체품과의 비교
| 파라미터 | 이 제품 | ADS825U | ADS826U | TLC5510I | AD9200ARS |
|---|---|---|---|---|---|
| Package | SO-28 / SSOP-28 | SO-28 | SO-28 | SO-28 | SOIC-28 |
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Analog Devices |
| Resolution | 10 bit | 10 bit | 10 bit | 10 bit | 10 bit |
| Sampling Rate | 40 MSPS | 40 MSPS | 60 MSPS | 20 MSPS | 20 MSPS |
| Supply Voltage | +5 V single | +5 V | +5 V | +5 V | +5 V / +3 V |
| Internal Reference | Yes | Yes | Yes | Yes | Yes |
주요 차별점
- Lowest power in TI 10-bit 40MSPS class (vs ADS826U)
- Fully integrated reference and track-and-hold (vs TLC5510I)
- Differential input capability (vs AD9200ARS)
설계 노트
Drive the ADS821 analog input from a low-impedance source or high-speed op-amp (e.g., OPA2670 for differential drive). The internal track-and-hold must settle within one 25 ns sample period (40 MSPS); a source impedance above a few hundred ohms will cause droop errors and SNR loss. Keep the input trace short, matched, and referenced to a clean analog ground plane.
Decouple every AVDD and DVDD pin with 0.1uF ceramics placed within 3-5 mm of the pin, plus 10uF bulk per rail. Partition analog and digital grounds under the SO-28 and join them at a single point beneath the ADC. Route the CLK line away from the analog input to avoid clock feedthrough artifacts in the output spectrum.
Do not exceed the 40 MSPS clock rate specified in the TI datasheet; pipelined performance (58 dB SNR, no missing codes) is guaranteed only within the rated range. Use the power-down pin during idle periods to cut consumption, but allow reference settling time after wake-up before resuming acquisition, or the first samples may be inaccurate.
At 380 mW on a +5V rail the ADS821 draws roughly 76 mA total; size linear regulators and thermal copper accordingly. For battery or portable instruments, assert power-down between acquisition bursts - the power-down feature is internal to the converter and eliminates the need for supply switching FETs.
규정 준수 정보
ADS821UG4 suffix indicates TI G4 (Pb-free) packaging; full RoHS/REACH certificates should be confirmed via TI product page.
