ATMEGA644P-20AU - 8-Bit AVR MCU 20MHz 64KB Flash TQFP-44 | Microchip
부품 번호: ATMEGA644P-20AU ✓ 활성| 수량 | 단가 | 합계 |
|---|---|---|
| 1 | $6.2 | $6.20 |
| 10 | $5.58 | $55.80 |
| 100 | $4.95 | $495.00 |
| 500 | $4.4 | $2,200.00 |
| 1,000 | $3.95 | $3,950.00 |
ATMEGA644P-20AU 개요
An 8-bit microcontroller is a self-contained computing IC that integrates a CPU core, program memory, data memory, and peripherals such as UARTs, timers, ADCs, and SPI/I2C interfaces on a single die. Within the power-management hierarchy of an embedded system, the MCU sits at the control layer, executing firmware that orchestrates sensors, actuators, and communication links. The AVR family, originally developed by Atmel and now part of Microchip Technology, executes most instructions in a single clock cycle, delivering approximately 1 MIPS per MHz.
Key features of the ATmega644P include the advanced AVR RISC architecture with 130 powerful instructions and 32 general-purpose working registers, up to 20 MIPS throughput at 20MHz, and two programmable serial USARTs. The P suffix denotes the enhanced variant with PicoPower-class low-power features and an additional USART compared with the base ATmega644.
Technical depth: the device integrates a 10-bit ADC, SPI and TWI (I2C) serial interfaces, multiple PWM-capable timers, an on-chip debug capability, and in-system programming (ISP) via the SPI interface. Self-programming FLASH enables boot-loader firmware updates in the field.
Typical applications include industrial control panels, motor control and power-supply supervision, metering and sensor-hub nodes, and legacy Arduino-compatible boards that use the ATmega644P core.
Design consideration: the 20MHz grade requires 4.5V to 5.5V operation; for 3.3V designs, derate the clock or choose a PicoPower ATmega644PA variant. Decouple AVCC and VCC separately for ADC accuracy.
This page synthesizes distributor pricing, drop-in alternatives, pinout data, and practical design notes not consolidated in the manufacturer datasheet.
드롭인 대체품: ATMEGA644P-20AU — 동일 패키지, 핀 호환. PCB 재작업이 필요한 다른 패키지 부품은 제외됩니다.
이 시리즈의 변형
다음과 드롭인 호환되는 동일 시리즈 모델: ATMEGA644P-20AU (동일 폼 팩터 및 풋프린트) — 차이점: ADC, Timer/Counters, Core Architecture, Package, EEPROM.
빠른 비교 도구 — 나란히 비교할 대체 부품을 선택하십시오:
ATMEGA644PA-AU
✅ 드롭인✓ 재고 있음
$4.61 / 개
데이터시트 보기 →ATMEGA644P-15AZ
✅ 드롭인 ⚠️ 사양 미검증✓ 재고 있음
$4.98 / 개
데이터시트 보기 →ATMEGA644-20AU
✅ 드롭인✓ 재고 있음
$4.96 / 개
데이터시트 보기 →ATMEGA1284P-AU
✅ 드롭인 ⚠️ 사양 미검증✓ 재고 있음
$4.65 / 개
데이터시트 보기 →ATMEGA644P-20AU 최대 정격 & 전기적 특성
| Core | AVR 8-bit RISC |
| Core Size | 8-Bit |
| 최대 클록 주파수 | 20 MHz |
| Program Memory Size | 64 KB (32K x 16) FLASH |
| Data RAM Size | 4 KB SRAM |
| EEPROM Size | 2 KB |
| Supply Voltage Range | 4.5 V to 5.5 V (20 MHz grade) |
| Number of USARTs | 2 |
| ADC Resolution | 10-bit |
| Peripherals | SPI, TWI (I2C), PWM timers, WDT, BOD |
| I/O Count | 32 |
| 패키지 | 44-TQFP (10x10 mm) |
| 실장 유형 | Surface Mount |
| 동작 온도 | -40C to +85C (industrial) |
| Throughput | Up to 20 MIPS at 20 MHz (approx. 1 MIPS/MHz) |
| Programming | In-System Programmable (ISP) via SPI |
| RoHS 상태 | Compliant (green package) |
ATMEGA644P-20AU 핀 구성
| 핀 1 | PB0 (XCK0/T0) — Port B bit 0 / USART0 external clock / Timer0 external clock |
| 핀 2 | PB1 (T1) — Port B bit 1 / Timer1 external clock |
| 핀 3 | PB2 (AIN0/INT2) — Port B bit 2 / analog comparator input 0 / external interrupt 2 |
| 핀 4 | PB3 (AIN1/OC0) — Port B bit 3 / comparator input 1 / Timer0 output compare |
| 핀 5 | PB4 (SS) — Port B bit 4 / SPI slave select |
| 핀 6 | PB5 (MOSI) — Port B bit 5 / SPI master output, slave input |
| 핀 7 | PB6 (MISO) — Port B bit 6 / SPI master input, slave output |
| 핀 8 | PB7 (SCK/OC0A) — Port B bit 7 / SPI clock / output compare |
| 핀 9 | RESET — Active-low reset input |
| 핀 10 | VCC — Digital supply voltage |
| 핀 11 | GND — Ground |
| 핀 12 | XTAL2 — Crystal oscillator output 2 |
| 핀 13 | XTAL1 — Crystal oscillator input 1 / external clock |
| 핀 14 | PD0 (RXD0) — Port D bit 0 / USART0 receive |
| 핀 15 | PD1 (TXD0) — Port D bit 1 / USART0 transmit |
| 핀 16 | PD2 (INT0) — Port D bit 2 / external interrupt 0 |
| 핀 17 | PD3 (INT1) — Port D bit 3 / external interrupt 1 |
| 핀 18 | PD4 (XCK1/OC1B) — Port D bit 4 / USART1 clock / Timer1 output compare B |
| 핀 19 | PD5 (OC1A) — Port D bit 5 / Timer1 output compare A |
| 핀 20 | PD6 (OC2B/ICP) — Port D bit 6 / Timer2 output compare B / Timer1 input capture |
| 핀 21 | PD7 (OC2A) — Port D bit 7 / Timer2 output compare A |
| 핀 22 | PC0 (SCL) — Port C bit 0 / TWI clock |
| 핀 23 | PC1 (SDA) — Port C bit 1 / TWI data |
| 핀 24 | PC2 (TCK) — Port C bit 2 / JTAG test clock |
| 핀 25 | PC3 (TMS) — Port C bit 3 / JTAG test mode select |
| 핀 26 | PC4 (TDO) — Port C bit 4 / JTAG test data output |
| 핀 27 | PC5 (TDI) — Port C bit 5 / JTAG test data input |
| 핀 28 | AVCC — ADC supply voltage |
| 핀 29 | GND — Ground |
| 핀 30 | PC6 (TOSC1) — Port C bit 6 / Timer oscillator input (32.768 kHz) |
| 핀 31 | PC7 (TOSC2) — Port C bit 7 / Timer oscillator output |
| 핀 32 | PA7 (ADC7) — Port A bit 7 / ADC channel 7 |
| 핀 33 | PA6 (ADC6) — Port A bit 6 / ADC channel 6 |
| 핀 34 | PA5 (ADC5) — Port A bit 5 / ADC channel 5 |
| 핀 35 | PA4 (ADC4) — Port A bit 4 / ADC channel 4 |
| 핀 36 | PA3 (ADC3) — Port A bit 3 / ADC channel 3 |
| 핀 37 | PA2 (ADC2) — Port A bit 2 / ADC channel 2 |
| 핀 38 | PA1 (ADC1) — Port A bit 1 / ADC channel 1 |
| 핀 39 | PA0 (ADC0) — Port A bit 0 / ADC channel 0 |
| 핀 40 | PE0 (PDI/RXD1) — Port E bit 0 / programming data input / USART1 receive |
| 핀 41 | PE1 (PDO/TXD1) — Port E bit 1 / programming data output / USART1 transmit |
| 핀 42 | PE2 (XCK0/AIN0) — Port E bit 2 / clock / comparator input |
| 핀 43 | PE3 (OC0A/AIN1) — Port E bit 3 / output compare / comparator input |
| 핀 44 | VCC — Digital supply voltage |
일반적인 애플리케이션
ATMEGA644P-20AU 적합 용도: 6 애플리케이션s: Industrial Control Panels, Embedded Sensor Hubs and Data Loggers, Motor Control and Power Supervision, Legacy Arduino-Compatible Boards (Sanguino class), Metering and Building Automation Terminals, Communication Bridges and Protocol Converters.
Industrial Control Panels
The ATMEGA644P-20AU fits industrial control and automation panels where its 4.5V-5.5V supply matches legacy 5V logic rails, and its -40C to +85C industrial temperature rating covers harsh cabinets. The dual USARTs simultaneously link to an RS-485/Modbus converter and an HMI or debug terminal, while the 10-bit ADC reads potentiometers, 4-20mA-derived voltages, and temperature channels. The 64KB FLASH accommodates ladder-logic interpreters or Modbus RTU stacks, and 4KB SRAM buffers communication frames. In-system programming via SPI allows field firmware updates without removing the MCU from the panel, reducing maintenance cost. As a 5V part it also drives relays and optocouplers directly without level shifting.
추천
Embedded Sensor Hubs and Data Loggers
For sensor hubs and data loggers, the ATMEGA644P-20AU combines a 10-bit ADC with SPI, TWI (I2C), and two USARTs, letting one MCU aggregate analog sensors, digital I2C/SPI devices, and a serial radio or RS-232 link. The 2KB EEPROM stores calibration constants and rolling log indexes that survive power loss, while 4KB SRAM provides ample FIFO buffering for burst acquisitions at the 20MHz core clock. The 64KB FLASH hosts both application code and a boot-loader for OTA-style updates over the serial link. Designers should route AVCC through an LC filter and sample with a stable ADC reference to reach datasheet ADC accuracy across the -40C to +85C range.
추천
Motor Control and Power Supervision
The ATMEGA644P-20AU suits small motor control and power-supply supervision tasks: hardware PWM timers generate drive waveforms for brushed DC and stepper motors, and fast interrupt latency at 20MHz closes current or speed loops in firmware. The 10-bit ADC monitors bus voltage, current-shunt amplifiers, and temperature sensors, while general-purpose I/O on Port B and Port D drives gate drivers or relay stages directly from the 5V rail. A watchdog timer with brown-out detection provides fail-safe recovery in mains-powered equipment. Because this is a 5V part, gate thresholds of classic MOSFET drivers are met without level shifters; the industrial temperature grade supports enclosed drives near thermal limits.
추천
Legacy Arduino-Compatible Boards (Sanguino class)
The ATMEGA644P-20AU is the classic core of Sanguino-class Arduino-compatible boards, chosen for its 64KB FLASH (twice the classic ATmega328) and 44-TQFP layout that exposes 32 I/O lines. Maker projects that outgrow ATmega328P memory limits - large NeoPixel frames, multi-serial sketches, or FAT-style logging - port with minimal code changes because the AVR core, ISP toolchain (avrdude), and Arduino bootloader flow are identical. Two USARTs allow USB-serial bridging plus a GPS or Bluetooth module concurrently. Boards run the MCU at 16MHz or the full 20MHz from a 5V rail; remember the 20MHz grade is specified only at 4.5V-5.5V, so 3.3V shields need level shifting.
추천
Metering and Building Automation Terminals
Energy meters, thermostats, and building automation terminals benefit from the ATMEGA644P-20AU's balance of memory and peripherals: 64KB FLASH holds energy-accumulation firmware and LCD menus, the 2KB EEPROM retains tariff tables and lifetime counters, and the TWI interface drives RTC chips and I2C displays while USART 0 or 1 talks to M-Bus or RS-485 backplanes. The 10-bit ADC samples current-transformer outputs for basic power measurement, and the brown-out detector protects metering integrity during brownouts. Industrial temperature rating permits mounted meter enclosures in unconditioned spaces. For battery-backed or energy-harvesting versions, select the ATMEGA644PA-AU whose PicoPower sleep currents dramatically extend battery life.
추천
Communication Bridges and Protocol Converters
With two independent hardware USARTs, the ATMEGA644P-20AU is a natural protocol converter: bridge RS-232 to RS-485, USB-serial to UART, or Modbus RTU to a custom serial protocol, at line rates comfortably handled by the 20MHz AVR core. SPI and TWI let the same device translate between serial and I2C/SPI buses, while 4KB SRAM buffers frame reassembly and packet queues without external RAM. The 64KB FLASH accommodates two protocol stacks plus a boot-loader for field-updatable mapping tables. Hardware flow control and multi-processor communication modes of the USARTs simplify robust link design; use 1% XTAL or internal calibration review to keep baud-rate error below 2%.
추천
추천 제품 요약
엔지니어링 참조 데이터: ATMEGA644P-20AU — 비교, 설계 지침 및 규정 준수 정보.
선택 가이드
대체품과의 비교
| 파라미터 | 이 제품 | ATMEGA644PA-AU | ATMEGA644P-15AZ | ATMEGA644-20AU | ATMEGA1284P-AU |
|---|---|---|---|---|---|
| Package | 44-TQFP (10x10 mm) | 44-TQFP (10x10 mm) - same | 44-TQFP (10x10 mm) - same | 44-TQFP (10x10 mm) - same | 44-TQFP (10x10 mm) - same |
| Brand | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology |
| Program FLASH | 64 KB | 64 KB | 64 KB | 64 KB | 128 KB |
| SRAM | 4 KB | 4 KB | 4 KB | 4 KB | 16 KB |
| Max Clock Frequency | 20 MHz | 20 MHz | 15 MHz | 20 MHz | 20 MHz |
| USARTs | 2 | 2 | 2 | 1 | 2 |
| New-Design Recommendation | No (mature; replaced by 644PA) | Yes (recommended replacement) | No | No (mature) | Yes (active family) |
주요 차별점
- Dual hardware USARTs in a 44-TQFP footprint (vs ATMEGA644-20AU)
- Legacy availability for existing 644P production (vs ATMEGA644PA-AU)
- Cost-optimized memory point versus larger family members (vs ATMEGA1284P-AU)
설계 노트
Supply decoupling and AVCC treatment are critical for ADC accuracy. Place 100nF ceramic capacitors at each VCC pin (pins 10 and 44) and at AVCC (pin 28), each with a low-ESL path to the nearest GND (pins 11, 29). Feed AVCC through an LC filter (10uH ferrite + 100nF/10uF) from the digital 5V rail so ADC readings are not corrupted by digital switching noise; connect AGND to the solid ground plane via a single low-impedance via. If using the internal 2.56V ADC reference, add 100nF on AREF and avoid loading it externally. Estimated: even at 20MHz with all ports toggling, active current stays within tens of mA, so a 5V/100mA budget per MCU is comfortable.
The 44-TQFP (10x10mm) uses a 0.8mm pitch, well within standard reflow capability, but breakout fanout determines signal quality. Keep the XTAL1/XTAL2 crystal loop (pins 12-13) within ~10mm of the pins, guard it with ground pour, and never route fast USART/PWM traces under the crystal net. For ISP programming, route MOSI/MISO/SCK/RESET to a standard 2x3 header; keep RESET (pin 9) pulled up 10k and add a 100nF to GND for robust external-reset behavior with programmers that toggle the line. Expose JTAG pads (PC2-PC5) if on-chip debugging is planned, since rework later on 0.8mm pitch is feasible but costly.
Three recurring mistakes with this part: (1) Operating at 20MHz below 4.5V - the 20MHz speed grade is specified only for 4.5V-5.5V; derate frequency at lower VCC or use the ATmega644PA. (2) Assuming two USARTs exist on the base ATmega644-20AU when substituting - the P variant's second USART (Port E, pins 40-41) is the key difference; code using RXD1/TXD1 will not compile or will misbehave on the non-P part. (3) Ignoring lifecycle status: Microchip marks the 644P as mature and points to the 644PA; designs finalized today should qualify ATMEGA644PA-AU as the production part and treat the 644P as a maintenance-order item.
규정 준수 정보
RoHS compliant green package per FindIC and Xecor data ('TQFP, IND TEMP, GREEN'). REACH and conflict-minerals declarations not stated in provided data - confirm via Microchip compliance portal.