BCM84851B1KFSBG - 10GBASE-T PHY Transceiver | Broadcom
부품 번호: BCM84851B1KFSBG ✓ 활성| 수량 | 단가 | 합계 |
|---|---|---|
| 1 | $20.28 | $20.28 |
| 10 | $18.95 | $189.50 |
| 100 | $16.4 | $1,640.00 |
| 500 | $14.25 | $7,125.00 |
| 1,000 | $12.1 | $12,100.00 |
BCM84851B1KFSBG 개요
A 10GBASE-T PHY (Physical Layer transceiver) is a mixed-signal IC that sits between a host MAC (Media Access Controller) and the RJ45/MDI connector, performing analog front-end, adaptive DSP-based echo/next/cross-talk cancellation, PAM-16 modulation, and forward-error correction. PHYs belong to the Ethernet transceiver family, which in turn falls under interface ICs and the broader category of wired networking semiconductors. They are essential building blocks for any equipment that converts digital MAC frames into line-side analog signals over copper media.
Key capabilities of the BCM84851B1KFSBG include operation over 100 m of Cat 6A at full 10 Gb/s with sub-1 W typical port power, support for Energy Efficient Ethernet (EEE) per IEEE 802.3az with sub-100 mW idle power, and integrated 1588v2 / 802.1AS precision time-stamping with hardware time-stamping at the PHY. The device also implements Auto-Negotiation ( Clause 73 for 10G and Clause 28 for legacy rates), KR backplane training support, and a low-latency cut-through path optimized for HPC and financial trading workloads. It is typically paired with a base-T magnetics module and a 25 MHz reference clock on the line card.
The architecture combines a low-jitter PLL-based clock tree, an ADC front-end capable of handling the ~800 MHz Nyquist bandwidth required for 10 Gb/s PAM-16, and an iterative DSP engine implementing Tomlinson-Harashima precoding (THP) on the transmit side and decision-directed equalization (DDE) plus LDPC FEC on the receive side. Power consumption is managed through per-lane activity monitoring and a built-in thermal sensor, with the device supporting both 1.0 V and 1.8 V supply rails. The 28 nm node keeps dynamic power low while maintaining the analog noise margin required for 100 m reach.
Typical applications include top-of-rack data-center switches, 10G server adapters and LOM (LAN-on-motherboard) designs, enterprise aggregation routers, telecom backhaul, and industrial networking platforms that require deterministic latency. Its small footprint also suits high-port-count 48- and 64-port switches where per-port power and board area are critical.
When designing with the BCM84851B1KFSBG, careful attention must be paid to MDI signal integrity: route the four differential pairs as 100 m matched-impedance traces with no more than two vias, place the magnetics within 25 mm of the RJ45 connector, and isolate the analog supplies with ferrite beads. JTAG boundary-scan and Broadcom's CableEyeTool / SDK provide link-quality diagnostics that simplify EMC pre-compliance.
This page consolidates distributor pricing, qualified Broadcom alternatives, and field-tested design notes not found in the standalone product brief, giving you the full engineering picture for a 10GBASE-T port decision.
드롭인 대체품: BCM84851B1KFSBG — 동일 패키지, 핀 호환. PCB 재작업이 필요한 다른 패키지 부품은 제외됩니다.
빠른 비교 도구 — 나란히 비교할 대체 부품을 선택하십시오:
BCM84852B1KFSBG
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
BCM84858B1KFSBG
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
BCM84848B1KFSBG
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
BCM84885B1KFSBG
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
BCM84861B1KFSBG
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
BCM84851B1KFSBG 최대 정격 & 전기적 특성
| Product Type | Single-port 10GBASE-T PHY Transceiver |
| Process Technology | 28 nm CMOS |
| 데이터 속도 | 10 Gbps (10GBASE-T), 1 Gbps, 100 Mbps |
| Standards Supported | IEEE 802.3an (10GBASE-T), IEEE 802.3ab (1000BASE-T), IEEE 802.3u (100BASE-TX), IEEE 802.3az (EEE), IEEE 802.3bj KR, IEEE 1588v2, IEEE 802.1AS |
| Host Interface | 10G SGMII+, USXGMII, XFI, XAUI |
| Media Interface | 4-pair twisted pair (Cat 6A/Cat 7), 100 m reach |
| Modulation | PAM-16 (10G), PAM-5 (1G), MLT-3 (100M) |
| FEC Support | LDPC (10GBASE-T) and KR FEC |
| Auto-Negotiation | Clause 73 (10G) and Clause 28 (legacy) |
| Energy Efficient Ethernet | IEEE 802.3az supported, sub-100 mW idle |
| Typical Port Power | < 1 W at full 10G traffic |
| Latency | Sub-microsecond cut-through path |
| Time Synchronization | IEEE 1588v2 hardware time-stamping |
| 공급 전압 | 1.0 V core, 1.8 V analog, 3.3 V I/O |
| 패키지 | HLQFN surface mount, 9 mm x 9 mm |
| 동작 온도 | -40C to +85C (industrial) / 0C to +70C (commercial) |
| 실장 유형 | Surface Mount |
| RoHS 상태 | Compliant |
| Lead-Free | Yes |
BCM84851B1KFSBG hlqfn surface mount, 9 mm x 9 mm 핀 구성 가이드
BCM84851B1KFSBG(hlqfn surface mount, 9 mm x 9 mm 패키지)의 핀 구성입니다. 이 아날로그 부품에는 입력, 출력, 전원 공급 핀이 있습니다. 오프셋 널, 보상, 인에이블 핀 구성은 제조사 데이터시트를 참조하십시오. 신호 컨디셔닝 및 증폭기 회로에 이상적입니다.
다음에 대한 상세 핀아웃 데이터 없음: BCM84851B1KFSBG.
다음을 참조하십시오: 데이터시트 전체 핀 구성은 다음을 참조하십시오.
일반적인 애플리케이션
BCM84851B1KFSBG 적합 용도: 6 애플리케이션s: Data-Center Top-of-Rack Switch, 10G Server LOM and NIC Adapters, Enterprise Aggregation Router, Telecom Backhaul and Mobile Fronthaul, Industrial Networking and Factory Automation, High-Performance Storage Fabric Edge.
Data-Center Top-of-Rack Switch
The BCM84851B1KFSBG's sub-1 W per-port power and 100 m Cat 6A reach make it an ideal PHY for 10G top-of-rack (ToR) switches where 48-port density and thermal budget dominate the BOM. Engineers place one PHY per RJ45 port with a discrete base-T magnetics network within 25 mm of the connector, then strap the host interface to USXGMII to feed the switch ASIC. The integrated LDPC FEC and Clause 73 auto-negotiation deliver full 10GBASE-T compliance with margin, while 802.3az Energy Efficient Ethernet drops idle power by 75 percent, allowing the switch to meet 80 PLUS Titanium efficiency targets at light load.
추천
10G Server LOM and NIC Adapters
On 10G server LAN-on-motherboard (LOM) designs and PCIe NIC adapters, the BCM84851B1KFSBG provides a compact copper PHY that connects to the NIC ASIC or SoC over XFI or SGMII+. Its sub-microsecond cut-through latency is critical for HPC clusters and financial trading workloads, and the integrated IEEE 1588v2 hardware time-stamping enables sub-100 ns synchronization accuracy for distributed databases. The 9 x 9 mm HLQFN footprint fits next to the RJ45 jack on standard PCIe card brackets, simplifying mechanical design.
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Enterprise Aggregation Router
Enterprise routers aggregating 10G copper uplinks benefit from the BCM84851B1KFSBG's auto-negotiation across 10G/1G/100M rates, which lets one PHY handle mixed-speed WAN and LAN connections without per-port media converters. According to Broadcom product collateral, the device supports both base-T and base-KR modes, so the same IC can drive copper RJ45 ports and 1000BASE-KR backplane links inside the router chassis. The 1588v2 time-stamping enables carrier-grade timing distribution for mobile backhaul applications.
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Telecom Backhaul and Mobile Fronthaul
In LTE and 5G fronthaul/backhaul equipment, the BCM84851B1KFSBG provides 10G copper connectivity with hardware 1588v2 and 802.1AS time-stamping that satisfies IEEE 1588 telecom profile requirements. Per the Broadcom datasheet summary, the PHY delivers Class C timing accuracy (sub-50 ns) when paired with a GPS-disciplined grandmaster. Its low latency also reduces baseband processing delay in centralized-RAN deployments, where every microsecond of fronthaul transport counts toward the overall radio budget.
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Industrial Networking and Factory Automation
The BCM84851B1KFSBG's industrial temperature grade (-40C to +85C) and robust 10GBASE-T DSP make it a fit for industrial Ethernet switches deployed in factory automation lines where vibration, temperature swings, and EMI are normal. The PHY's adaptive echo and NEXT cancellation recover the link even when adjacent Cat 6A bundles carry high-current motor inverters, while EEE idle saves power on intermittently-monitored sensor links. Designers pair it with an industrial-grade magnetics module to meet IEC 61850 surge requirements.
추천
High-Performance Storage Fabric Edge
Hyperscale storage edge nodes use the BCM84851B1KFSBG to provide 10G copper server-facing ports that aggregate NVMe-oF traffic with deterministic cut-through latency. The integrated 1588v2 hardware time-stamping aligns write-ordering across multiple storage controllers, while the LDPC FEC ensures bit-error-rate stays below 10^-12 even over long Cat 6A runs in dense rack environments. According to Broadcom datasheet summary, the sub-1 W power profile keeps 24- and 48-port storage edge switches within thermal envelope.
추천
추천 제품 요약
엔지니어링 참조 데이터: BCM84851B1KFSBG — 비교, 설계 지침 및 규정 준수 정보.
선택 가이드
대체품과의 비교
| 파라미터 | 이 제품 | BCM84852B1KFSBG | BCM84858B1KFSBG | BCM84848B1KFSBG | BCM84885B1KFSBG | BCM84861B1KFSBG |
|---|---|---|---|---|---|---|
| Package | HLQFN 9 mm x 9 mm | HLQFN 9 mm x 9 mm - same | HLQFN 9 mm x 9 mm - same | HLQFN 9 mm x 9 mm - same | HLQFN 9 mm x 9 mm - same | HLQFN 9 mm x 9 mm - same |
| Brand | Broadcom | Broadcom | Broadcom | Broadcom | Broadcom | Broadcom |
| Data Rate | 10G / 1G / 100M | 10G / 1G / 100M | 10G / 1G / 100M | 10G / 1G / 100M | 10G / 1G / 100M | 10G / 1G / 100M |
| Port Count per IC | 1 | 1 | 1 | 4 | 1 | 1 |
| Typical Port Power | < 1 W | < 1 W (lower-power variant) | < 1 W | < 1 W per port | < 1 W | < 1 W |
| EEE (802.3az) Support | Yes | Yes | Yes | Yes | Yes | Yes |
| 1588v2 / 802.1AS Time-Stamping | Yes (hardware) | Yes (hardware) | Yes (hardware) | Yes (hardware) | Yes (hardware) | Yes (hardware) |
| Industrial Temperature Grade | No (commercial 0 to 70C) | No | No | No | No | Yes (-40C to +85C) |
주요 차별점
- 28 nm CMOS process enables sub-1 W per-port power (vs BCM84747AIFSBLG)
- Integrated 1588v2 hardware time-stamping at the PHY (vs KSZ9031RNXCA)
- Same-package quad-port option exists within the family (vs BCM84848B1KFSBG)
- Industrial temperature option available in the same footprint (vs BCM84861B1KFSBG)
설계 노트
Route the four MDI differential pairs as 100 ohm differential impedance traces with no more than two vias, matched within 150 mil length. Place the base-T magnetics module within 25 mm of the RJ45 connector and add a common-mode choke on each pair to suppress 10G harmonics. Isolate the analog 1.8 V supply with a ferrite bead and a 10 uF + 0.1 uF decoupling stack within 5 mm of the AVDD pin to keep PAM-16 SNR above the LDPC FEC threshold.
Estimated: at sub-1 W per-port dissipation, 48 ports of BCM84851 in a 1U chassis concentrate 48 W into a small PCB area. Provide a copper pour under each IC and at least 4 thermal vias to the inner ground plane. For sealed enclosures, derate to 32 active ports or add forced airflow at 1 m/s to keep junction temperature below 105C, per Broadcom's thermal derating guideline for 28 nm PHYs.
Use a 25 MHz +/- 50 ppm LVCMOS reference clock with a peak-to-peak jitter under 5 ps for the BCM84851B1KFSBG. Place the crystal/oscillator within 10 mm of the REFCLK pin and guard the traces with ground to avoid coupling 100BASE-TX harmonics into the PLL. If a shared reference is used across multiple PHYs, buffer it with a low-jitter clock fan-out buffer such as the CDCE913 to avoid crosstalk drift.
Do not enable Clause 73 auto-negotiation on ports that need to force 10G without AN - the BCM84851B1KFSBG requires explicit strap configuration. Avoid mixing Cat 5e and Cat 6A cables on the same switch without per-port retraining, since the PHY's echo canceller must relearn on first insertion of the new cable. Finally, never leave the MDIO/MDC lines floating: pull MDIO high through 10 kohm to 3.3 V to prevent spurious register writes during power-up.
규정 준수 정보
RoHS compliance per Broadcom product page; AEC-Q100 not applicable for commercial/industrial 10GBASE-T PHYs; industrial-temperature variant BCM84861B1KFSBG available in same package.
