CD4046BE - 2.4MHz Micropower CMOS PLL IC | Texas Instruments
부품 번호: CD4046BE ✓ 활성| 수량 | 단가 | 합계 |
|---|---|---|
| 1 | $0.4105 | $0.41 |
| 10 | $0.4105 | $4.11 |
| 100 | $0.4105 | $41.05 |
| 500 | $0.4105 | $205.25 |
| 1,000 | $0.4105 | $410.50 |
CD4046BE 개요
A phase-locked loop is a feedback-control system in which a voltage-controlled oscillator is adjusted until a generated signal matches the phase relationship of a reference input. Within the CD4046B family, the low-power linear VCO and alternative phase-comparator outputs allow different loop architectures to be selected. The CD4046BE therefore combines oscillator and detector functions that would otherwise require separate discrete blocks, reducing component count in clock multiplication, demodulation, frequency synthesis, tone generation, and signal-conditioning circuits.
The verified source identifies the CD4046BE as a CMOS micropower PLL with a 2.4 MHz maximum operating frequency, a 3 V to 18 V supply range, and approximately 10 mA supply current in the comparison data. It is offered in a 16-DIP package with a 0.300-inch pin pitch and 7.62 mm lead spacing. The two internal phase comparators and shared input amplifier provide implementation flexibility, but loop stability still depends on correct external resistor, capacitor, filtering, and feedback selections.
Architecturally, the chip separates signal generation from phase detection. The linear VCO responds to its control voltage, while the phase-comparator sections generate correction information for the feedback loop. Comparator I is suited to positive-edge locking, whereas Comparator II supports zero-degree or 180-degree phase comparison depending on its configuration. Designers must follow the manufacturer datasheet for exact comparator logic, output states, operating limits, and timing because those details were not fully present in the supplied source text.
Typical uses include FM and FM-to-AM demodulation, frequency synthesis, tone decoding, frequency multiplication, scanning or sweep generation, and low-frequency clock generation. The part is particularly relevant when variable frequency or phase correction is required and a conventional fixed-frequency oscillator is insufficient. Its CMOS micropower architecture favors low-power signal-path and control applications, provided the external loop network is designed for the intended frequency and supply voltage.
The most important design consideration is loop-component validation. Keep the VCO timing network and feedback-path components close to the device, use the datasheet's recommended topology, and verify acquisition range, lock range, ripple, and phase error on the intended prototype. Component tolerances and parasitic capacitance can materially affect behavior at higher frequencies. Because the verified material does not provide complete timing or pin-function tables, engineers should obtain the manufacturer datasheet before release to production.
This page combines distributor availability, verified family-level specifications, sourcing information, replacement constraints, and practical PLL design guidance. It distinguishes confirmed data from missing parameters while preserving the key advantage of CD4046BE: an integrated CMOS PLL and VCO in a standard 16-pin DIP package.
드롭인 대체품: CD4046BE — 동일 패키지, 핀 호환. PCB 재작업이 필요한 다른 패키지 부품은 제외됩니다.
이 시리즈의 변형
다음과 드롭인 호환되는 동일 시리즈 모델: CD4046BE (동일 폼 팩터 및 풋프린트) — 차이점: Mounting Type, Package, Product Type.
빠른 비교 도구 — 나란히 비교할 대체 부품을 선택하십시오:
MC14046BE
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
MC14046B
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
HEC4046B
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
CD4046B
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
HEF4046B
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
CD4046BE 사양
| Product Type | CMOS micropower phase-locked loop (PLL) IC |
| Maximum Frequency | 2.4 MHz |
| Supply Voltage Range | 3 V to 18 V |
| 공급 전류 | Approximately 10 mA |
| Oscillator Architecture | Low-power linear voltage-controlled oscillator (VCO) |
| Phase Comparator Count | 2 |
| Input Amplifier | Common signal-input amplifier |
| Comparator Input | Common comparator input |
| 패키지 | 16-DIP |
| Package Pitch | 0.300 in (7.62 mm) |
| Technology | CMOS |
| 실장 유형 | Through-hole dual in-line |
| Power Class | Micropower |
| Phase Comparator Type | Two different phase comparators |
| RoHS 상태 | unknown |
| REACH Status | unknown |
CD4046BE 0.300 in (7.62 mm) 핀 구성 가이드
CD4046BE(0.300 in (7.62 mm) 패키지)의 핀 구성입니다. 핀 번호, 기능, 연결 다이어그램은 제조사 데이터시트에 정의되어 있습니다. 정확한 풋프린트와 솔더링 지침은 해당 문서를 참조하십시오.
다음에 대한 상세 핀아웃 데이터 없음: CD4046BE.
다음을 참조하십시오: 데이터시트 전체 핀 구성은 다음을 참조하십시오.
일반적인 애플리케이션
CD4046BE 적합 용도: 6 애플리케이션s: FM Demodulation, Frequency Synthesis, Frequency Multiplication, Tone Decoding, Variable-Frequency Signal Generation, Clock Synchronization.
FM Demodulation
CD4046BE suits FM demodulation because it combines a 2.4 MHz-capable low-power linear VCO with phase-detection circuitry in one 16-DIP package. Connect the received signal through the appropriate input network and configure one phase comparator in a feedback loop so the VCO follows the carrier. The verified 3 V to 18 V supply range allows operation at multiple logic-compatible rails, but loop time constants must be selected for the carrier range. Test capture behavior, distortion, ripple, and recovery after signal loss rather than assuming ideal lock.
추천
Frequency Synthesis
CD4046BE can form a variable-frequency clock generator when a reference must be compared with a VCO-derived signal. Its two phase comparators provide choices for edge-sensitive or zero/180-degree phase relationships, while the low-power CMOS VCO adjusts frequency through its control voltage. The verified 2.4 MHz maximum device frequency and 3 V to 18 V supply range provide useful design bounds, although actual tuning range depends on timing components and supply. Validate lock range, phase jitter, acquisition time, and output stability over temperature.
추천
Frequency Multiplication
CD4046BE can be used in a multiplication arrangement where a divided VCO output is compared with the original reference and the loop corrects phase until the frequencies agree. The integrated VCO and phase comparators reduce the block count compared with separate oscillator and detector designs. Its 2.4 MHz verified maximum frequency supports many low- and moderate-speed clock tasks, but divider behavior and harmonic selection must be analyzed. Breadboard testing should verify phase margin and whether unwanted harmonics prevent reliable lock.
추천
Tone Decoding
CD4046BE can decode a target tone by configuring the VCO and feedback network to favor a selected frequency. When the received frequency matches the loop's operating point, the phase detector produces the required timing information for downstream decision logic. The shared input amplifier and two comparator options allow the circuit to be adapted to different detection approaches. Because the supplied snippets omit center-frequency equations, calculate timing components from the manufacturer guidance and test adjacent-frequency rejection, capture bandwidth, and response time.
추천
Variable-Frequency Signal Generation
CD4046BE is appropriate when an adjustable frequency is more useful than a fixed clock. The low-power linear VCO converts its control voltage into a variable-frequency output, and the phase-comparator sections can close a feedback loop around that oscillator. This arrangement is useful in audio test equipment, scanning circuits, and controllable tone sources. Keep the timing resistor and capacitor physically short to reduce parasitic effects, and verify available tuning range across the intended supply voltage because the listed 3 V to 18 V range is not itself a guaranteed VCO operating span.
추천
Clock Synchronization
CD4046BE can synchronize a locally generated VCO signal to an external clock by feeding phase-error information back to the oscillator control path. The 16-DIP package provides a straightforward implementation for through-hole control boards, while the approximately 10 mA verified supply current aligns with low-power CMOS logic. The loop must be tuned for the expected clock frequency and jitter budget. Confirm lock time, cycle-to-cycle phase variation, and behavior during input interruption before using it as a system timing source.
추천
추천 제품 요약
엔지니어링 참조 데이터: CD4046BE — 비교, 설계 지침 및 규정 준수 정보.
선택 가이드
대체품과의 비교
| 파라미터 | 이 제품 | MC14046BE | MC14046B | HEC4046B | CD4046B | HEF4046B |
|---|---|---|---|---|---|---|
| Brand | Texas Instruments | onsemi | onsemi | onsemi | Texas Instruments | NXP Semiconductors |
| Package | 16-DIP | 16-DIP | 16-DIP | 16-DIP | 16-DIP | 16-DIP |
| Product Type | CMOS micropower PLL | PLL | PLL | PLL | CMOS micropower PLL | PLL |
주요 차별점
- Verified distributor sourcing (vs CD4046B)
- Integrated dual-comparator PLL architecture (vs MC14046B)
- Clearly identified 16-DIP implementation (vs HEF4046B)
설계 노트
Place the VCO timing components and loop-filter connections directly beside the relevant CD4046BE pins, and keep feedback routing compact. The supplied evidence does not provide the complete pin map, so consult the current Texas Instruments CD4046B datasheet before laying out the board. Minimize long traces around the phase comparator because parasitic capacitance can alter oscillator behavior and loop stability.
Do not infer a universal replacement from the CD4046-family name. The verified evidence does not establish all alternative pin mappings, supply limits, VCO ranges, or comparator timings. Before substituting MC14046B, HEC4046B, CD4046B, or HEF4046B, compare every lead and recalculate external R-C or C1 values against the selected manufacturer's datasheet.
Decouple the supply with local high-frequency and bulk capacitance selected from the manufacturer guidance. The verified supply-current reference is approximately 10 mA, but actual demand depends on the operating state and frequency. Keep the 3 V minimum in mind when designing a low-voltage system, and validate startup and lock behavior across the intended supply range rather than assuming performance at the 18 V maximum applies at every voltage.
Validate capture range, lock range, jitter, and harmonic behavior on hardware. A nominal 2.4 MHz maximum does not guarantee stable VCO operation at every frequency or supply voltage. Component tolerance, parasitic capacitance, comparator configuration, and loop gain can prevent lock even when the calculated frequency appears correct. Document test conditions and external component values for production traceability.
규정 준수 정보
The verified snippets do not provide definitive RoHS, REACH, AEC-Q100, lead-free, halogen-free, or conflict-minerals statements for CD4046BE.
