CD4059AE - Programmable Divide-by-N Counter | Texas Instruments
부품 번호: CD4059AE ✓ 활성CD4059AE 개요
A programmable divide-by-N counter is a clock-and-timing logic device that divides an input pulse train by a selectable integer. It belongs to the counter hierarchy, which includes frequency dividers and timing counters, and ultimately falls within digital logic ICs and clock-and-timing semiconductor categories. This architecture makes the CD4059AE useful whenever a stable reference frequency must be reduced to a lower derived frequency without changing the original signal source.
The 16 jam inputs establish the divide ratio, allowing division by any number from 3 through 15,999. A divide-by-16 counter is therefore the conventional implementation, while the wider jam-input arrangement supports programmable ratios without adding a separate binary counter. The single output pulse is one clock cycle wide, making its relationship to the input timing straightforward to analyze and measure.
The CD4059AE uses positive-edge counting, so the active transition is the rising edge of the clock waveform. Designers must account for setup and hold requirements around the jam inputs because changing the programmed divide value while the counter is operating can produce a transient output disturbance. The wide programmable range supports synthesized timing, pulse-rate division, periodic event generation, and frequency scaling.
Typical applications include digital timer and counter modules, industrial pulse-generation circuits, clock dividers in control equipment, and repetitive event-rate reduction in test systems. The fixed-width output can trigger downstream counters or timing stages, while the jam inputs allow the system to change its operating rate under supervisory control.
For dependable operation, use the manufacturer's pin-description table when assigning PCB signals and verify every jam-input state required by the desired division ratio. Confirm clock edge timing and output loading against the device limits, then provide suitable bypassing and a clean common ground reference. This page combines programming guidance, practical circuit considerations, and packaging information to support faster design review and sourcing.
The CD4059AE remains a useful choice when a 24-lead through-hole programmable divider is preferred over a smaller logic device, particularly when the design benefits from direct jam programming across the full 3-to-15,999 ratio. Its 24-pin footprint requires adequate board spacing, so compact modern equipment may require a different counter architecture rather than a forced package substitution.
드롭인 대체품: CD4059AE — 동일 패키지, 핀 호환. PCB 재작업이 필요한 다른 패키지 부품은 제외됩니다.
이 제품에는 사용 가능한 드롭인 대체품이 없습니다.
대체품 요청CD4059AE 사양
| Device Type | CMOS programmable divide-by-N counter |
| Counter Element | 1 element |
| Counting Direction | Down-counter |
| Counting Edge | Positive edge |
| Programmable Divide Ratio | 3 to 15,999 |
| Jam Input Count | 16 inputs |
| Counter Width | 16 bit |
| Output Pulse Width | 1 clock cycle |
| Output Drive Capability | TTL-compatible drive |
| Logic Family | CMOS |
| Package Type | 24-lead dual-in-line plastic package |
| Package Pin Count | 24 pins |
| 실장 유형 | Through-hole |
| 동작 온도 | -55 °C to +125 °C |
| 동작 온도 범위 | -55 °C to +125 °C |
CD4059AE 24 pins 핀 구성 가이드
CD4059AE(24 pins 패키지)의 핀 구성입니다. 핀 번호, 기능, 연결 다이어그램은 제조사 데이터시트에 정의되어 있습니다. 정확한 풋프린트와 솔더링 지침은 해당 문서를 참조하십시오.
다음에 대한 상세 핀아웃 데이터 없음: CD4059AE.
다음을 참조하십시오: 데이터시트 전체 핀 구성은 다음을 참조하십시오.
일반적인 애플리케이션
CD4059AE 적합 용도: 6 애플리케이션s: Programmable Digital Timer, Industrial Pulse-Rate Reduction, Clock Divider for Control Equipment, Periodic Event Generator, Test and Measurement Trigger Source, Legacy CD4000-System Expansion.
Programmable Digital Timer
The CD4059AE fits digital timer designs that require a selected clock frequency to be reduced by a fixed integer before driving a display, event counter, or elapsed-time stage. Its programmable division range of 3 to 15,999 allows one counter family to support several timing bases, while 16 jam inputs establish the selected ratio. The single output pulse remains one clock cycle wide, providing a defined transition for the next timing stage. In a timer implementation, use a clean oscillator source, preserve required setup and hold conditions around the jam inputs, and verify the maximum clock rate against the manufacturer electrical characteristics.
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Industrial Pulse-Rate Reduction
For industrial pulse-rate reduction, the CD4059AE can divide a repetitive sensor or machine-event signal by a programmed value from 3 to 15,999 before the signal reaches a slower monitoring stage. Positive-edge counting allows the circuit to operate directly from a suitable pulse source, and the fixed one-clock-cycle output gives downstream logic a defined event shape. Because machine environments can introduce noisy or irregular edges, use conditioning appropriate to the source and validate setup, hold, and reset behavior. The 24-lead DIP package also supports repairable and instrument-oriented equipment where through-hole serviceability is valuable.
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Clock Divider for Control Equipment
The CD4059AE serves as a programmable clock divider when a controller requires a lower periodic rate derived from a fixed system oscillator. With division available from 3 through 15,999, the same device can support different update intervals, task rates, or sampling triggers without requiring a separate programmable counter. The positive-edge input and one-cycle output simplify edge-to-edge timing analysis. Designers should establish the desired jam-input state before starting the divider and confirm that the source oscillator and output load satisfy the manufacturer timing and electrical limits.
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Periodic Event Generator
A CD4059AE-based periodic event generator uses the divided clock to trigger a flip-flop, one-shot, counter, or downstream logic stage at a reduced and predictable rate. The one-clock-cycle output width gives the receiving circuit a repeatable pulse rather than a continuously asserted level. The broad 3-to-15,999 divide range supports coarse timing divisions for beacon, relay, sampling, or maintenance systems. Use a debounced control path for rate changes, and avoid changing the jam inputs in a way that produces an unintended trigger during the transition.
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Test and Measurement Trigger Source
The CD4059AE can create a predictable trigger rate in bench equipment by dividing a reference oscillator and feeding the one-cycle output into a measurement or sequencing circuit. Its programmable ratio allows a single reference frequency to produce several trigger bases, reducing the number of oscillators required by an instrument. The 24-lead DIP format is useful in legacy laboratory equipment and repair platforms where an existing socket-compatible footprint is important. Validate pulse timing at the selected divide ratio, use a low-noise reference source, and ensure the connected instrument receives a signal meeting its trigger-level requirements.
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Legacy CD4000-System Expansion
The CD4059AE is well suited to extending a legacy CD4000-series logic design that already uses through-hole CMOS parts and requires programmable division. Its jam-programmable architecture permits multiple divide ratios without adding a conventional binary preset counter, while the single output integrates naturally into existing TTL-compatible logic chains. The 24-lead DIP package supports hand assembly, prototyping, and repair of older equipment. When replacing a failed device, verify the original board's supply voltage, clock amplitude, jam-input wiring, and pin orientation against the manufacturer pin-description table.
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추천 제품 요약
엔지니어링 참조 데이터: CD4059AE — 비교, 설계 지침 및 규정 준수 정보.
선택 가이드
설계 노트
Do not treat a different CD4059A package suffix as a drop-in substitute. CD4059AE uses a 24-lead DIP package, while the M and M96 suffixes use small-outline packages. Verify the physical footprint and pin numbering before any replacement. Texas Instruments also notes that there is no direct pin-to-pin CD4059A replacement and that the CD74HC4059 does not have TTL-compatible inputs, so a functional substitution requires a separate engineering review.
Use the manufacturer's pin-description table when assigning the 24 signals, and place the clock and jam-input traces away from high-current switching paths. Keep the clock source connection short and provide a common ground reference to the device and surrounding logic. Because changing the 16 jam-input states alters the division ratio, route configuration traces so they can be driven reliably and held at valid levels when the divider is expected to operate.
Account for positive-edge counting at every stage of the timing path. The output pulse is one clock cycle wide, so source resistance, capacitance, and the next device's input characteristics determine the usable pulse margin. Use a clean clock source and avoid long branches from oscillator or pulse-generation circuitry. Validate the operating division ratio and load arrangement with the electrical limits in the manufacturer datasheet before committing the layout.
규정 준수 정보
The CD4059AE is a legacy CMOS logic IC and is not an automotive-qualified AEC-Q100 product. RoHS, REACH, lead-free, halogen-free, and conflict-minerals status were not established from the cited product pages.
