CS5126-KL - 16-Bit 100 kHz Stereo ADC | Cirrus Logic
부품 번호: CS5126-KL ✓ 활성CS5126-KL 개요
An audio ADC is a mixed-signal semiconductor that converts left- and right-channel analog audio into 16-bit digital samples for storage, transmission, mixing, or playback. Within the broader hierarchy, the CS5126-KL is an ADC and data-converter IC, while its analog front end, sampling system, and serial output place it specifically in the digital-audio converter category. Its dual-channel and high-speed modes let one component serve stereo playback, recording, broadcast, communications, and consumer-electronics systems.
Key verified features include 16-bit resolution, two-channel operation, sampling rates up to 50 kHz per channel, and single-channel operation up to 100 kHz. The -KL ordering is associated with the 28-pin PLCC package identified by distributor and datasheet-index records. According to the available datasheet descriptions, the converter can also provide four digital output signals—SSH1, SSH2, TRKL, and TRKR—for controlling external sample-and-hold amplifiers when simultaneous sampling is required.
The CS5126 family uses a CMOS implementation and successive-approximation architecture. Successive approximation converts each sampled analog level through successive bit decisions, producing a 16-bit result for digital-audio processing. Separate left and right channel data paths support conventional stereo operation, while the digital outputs offer additional control for synchronized external sampling arrangements. The supplied records do not specify input-referred noise, distortion, dynamic range, clock frequency, or analog supply requirements.
Typical uses include professional and consumer audio capture, digital mixing consoles, multimedia playback equipment, audio communications, broadcast processing, and stereo measurement systems. In a stereo source, the converter can sample both channels at 50 kHz each; for a single high-rate signal path, it can operate at up to 100 kHz. This flexibility allows the same converter to address standard-rate audio streams or faster single-channel acquisition requirements.
Designers should preserve the converter’s specified analog and digital grounding strategy, provide compliant clocking and external bypass capacitors, and treat the analog input path as sensitive to noise. When simultaneous left and right conversion is required, the SSH1, SSH2, TRKL, and TRKR outputs can control external sample-and-hold circuitry. Detailed timing, electrical limits, and pin-level connections must be confirmed against the manufacturer datasheet before layout release.
This page consolidates verified distributor availability, package and conversion-mode information, source links, application guidance, and explicit data gaps. It also distinguishes the supported stereo 50 kHz-per-channel configuration from the 100 kHz single-channel mode, helping engineers plan signal-chain bandwidth without inferring unsupported performance figures.
드롭인 대체품: CS5126-KL — 동일 패키지, 핀 호환. PCB 재작업이 필요한 다른 패키지 부품은 제외됩니다.
이 제품에는 사용 가능한 드롭인 대체품이 없습니다.
대체품 요청CS5126-KL 최대 정격 & 전기적 특성
| Converter Type | Successive-approximation ADC |
| 분해능 | 16 bit |
| Architecture | CMOS |
| Channel Count | 2 channels |
| Maximum Stereo Sampling Rate | 50 kHz per channel |
| Maximum Single-Channel Sampling Rate | 100 kHz |
| Digital Output Signals | 4 signals: SSH1, SSH2, TRKL, and TRKR |
| External Sample-and-Hold Control | Supported through SSH1, SSH2, TRKL, and TRKR |
| 패키지 | 28-pin PLCC |
| Package Abbreviation | PQCC28 / LCC-28 |
| 실장 유형 | Surface mount |
| 인터페이스 유형 | Serial access |
| Primary Function | Stereo or monaural digital-audio conversion |
CS5126-KL pqcc28 / lcc-28 핀 구성 가이드
CS5126-KL(pqcc28 / lcc-28 패키지)의 핀 구성입니다. 이 아날로그 부품에는 입력, 출력, 전원 공급 핀이 있습니다. 오프셋 널, 보상, 인에이블 핀 구성은 제조사 데이터시트를 참조하십시오. 신호 컨디셔닝 및 증폭기 회로에 이상적입니다.
다음에 대한 상세 핀아웃 데이터 없음: CS5126-KL.
다음을 참조하십시오: 데이터시트 전체 핀 구성은 다음을 참조하십시오.
일반적인 애플리케이션
CS5126-KL 적합 용도: 6 애플리케이션s: Stereo Audio Capture, Digital Mixing Console, Broadcast Audio Processing, Audio Communications Terminal, Single-Channel High-Rate Acquisition, Consumer Audio Interface.
Stereo Audio Capture
The CS5126-KL fits stereo recording front ends because it converts two analog channels at up to 50 kHz per channel with 16-bit resolution. It can sit between line-level audio inputs and a digital audio processor, with each channel handled by the converter's stereo configuration. The two-channel mode avoids using separate converters when both program channels must be digitized. Its SSH1, SSH2, TRKL, and TRKR outputs can also coordinate external sample-and-hold circuits when exact channel timing is important. The supplied data does not state SNR, distortion, input range, or clock limits, so those values must be confirmed before fixing analog gain and front-end filtering.
추천
Digital Mixing Console
The CS5126-KL is applicable to multichannel mixing and routing equipment when a 16-bit audio ADC is sufficient. Two input channels can be sampled at 50 kHz per channel, allowing stereo buses, monitor paths, or effect returns to enter a digital processing chain. The serial interface keeps the digital connection practical for audio-oriented processors, while external sample-and-hold control provides additional implementation flexibility. In a console, clean analog grounding, short signal paths, and compliant bypass networks remain essential. Because the verified records do not provide channel-to-channel isolation, latency, or converter dynamic range, those specifications should be checked in the manufacturer datasheet before architecture sign-off.
추천
Broadcast Audio Processing
Broadcast and communications equipment can use the CS5126-KL to convert stereo program audio into a 16-bit digital representation at 50 kHz per channel. This capability fits channels that must preserve conventional audio bandwidth while moving into DSP-based mixing, compression, routing, or transmission stages. The device can also operate in a single-channel mode up to 100 kHz when a higher-rate isolated path is needed. Designers should account for the converter's analog front-end requirements, reference quality, and supported clocking arrangement. Exact conversion time, channel isolation, and permissible input level are not present in the supplied search data and therefore must be verified from the full manufacturer datasheet.
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Audio Communications Terminal
The CS5126-KL can serve as the conversion stage in an audio communications terminal that accepts a stereo microphone or line-level source and supplies digital samples to a signal processor. Its 16-bit resolution is appropriate for 50 kHz-per-channel audio, while the serial output supports integration with digital audio logic. In a communications design, analog input filtering and grounding are critical for preventing high-frequency interference from reaching the converter. The external sample-and-hold outputs can support timing-controlled acquisition when the system requires coordinated left and right sampling. Available verification data does not identify recommended microphone amplifiers or codec MPNs, so companion components require separate circuit-level selection.
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Single-Channel High-Rate Acquisition
The CS5126-KL can be configured for one channel at up to 100 kHz when the signal chain requires faster sampling than the 50 kHz-per-channel stereo mode. This makes the device relevant to specialized audio measurement, synchronized acquisition, or dual-purpose conversion designs that use one channel in high-rate mode and another mode in stereo. The converter's four digital outputs can coordinate external sample-and-hold amplifiers where simultaneous acquisition is required. Designers must confirm the valid clock relationships, conversion timing, and analog bandwidth in the manufacturer datasheet; these values were not included in the supplied snippets and should not be inferred from the maximum sampling-rate statement alone.
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Consumer Audio Interface
The CS5126-KL is suitable for a stereo consumer-audio interface that converts left and right analog inputs into 16-bit digital samples. In such a system, it can operate at 50 kHz per channel and feed a digital processor, storage engine, or transmission stage. The 28-pin PLCC package supports established through-hole-style PCB assembly rather than requiring a compact leadless land pattern. Implementation should preserve the manufacturer's recommended analog and digital layout practices and include the required bypass components. The verified information does not specify power-supply levels, clock frequency, or digital interface timing, so those details must be obtained from the full datasheet before schematic and layout approval.
추천
엔지니어링 참조 데이터: CS5126-KL — 비교, 설계 지침 및 규정 준수 정보.
선택 가이드
대체품과의 비교
| 파라미터 | 이 제품 |
|---|---|
| Package | 28-pin PLCC |
| Brand | Cirrus Logic |
| Resolution | 16 bit |
| Channel Count | 2 channels |
| Stereo Sampling Rate | Up to 50 kHz per channel |
| Single-Channel Sampling Rate | Up to 100 kHz |
| Converter Architecture | Successive approximation |
| Process Technology | CMOS |
| Digital Interface | Serial access |
| External Sample-and-Hold Outputs | SSH1, SSH2, TRKL, and TRKR |
| Verified Unit Price | $62.9689 as of 2026-10-29 |
주요 차별점
- Single converter supports two operating-rate configurations (vs CS5126-KP)
- Explicit control for external sample-and-hold amplifiers (vs CS5126-KP)
- Documented stereo ADC use case (vs Generic audio ADC alternatives)
설계 노트
Keep the analog input path short and place converter bypass components close to their specified package pins. Separate sensitive analog routing from digital clock and serial-output traces, and use the package pin assignments in the manufacturer datasheet to determine return paths. The verified data confirms a 28-pin PLCC package but does not provide the complete pin table, so the layout must not be released from package outlines or generic assumptions.
Use the manufacturer-defined clock arrangement and preserve all specified bypass capacitance before evaluating signal integrity. The CS5126-KL supports two-channel sampling to 50 kHz per channel or one-channel sampling to 100 kHz, but those maximum rates do not establish the required clock amplitude, timing margins, or permissible loading. Confirm those limits from the complete datasheet and probe the installed circuit at the relevant operating mode.
Do not treat the CS5126-KP or other functional ADC devices as drop-in replacements without verifying the 28-pin PLCC footprint and pin-by-pin assignments. The available cross-reference results establish family relationships but do not prove package or pin compatibility. For a replacement, compare serial-interface timing, supply rails, clocking, analog input range, conversion latency, and the SSH1, SSH2, TRKL, and TRKR control functions.
규정 준수 정보
The supplied product and distributor records do not explicitly state RoHS, REACH, AEC-Q100, lead-free, halogen-free, or conflict-minerals status. These fields remain unknown rather than being inferred from the package or manufacturer identity.
