DG401CJ+ - Dual 45 Ohm SPST Analog Switch | Analog Devices
부품 번호: DG401CJ+ ✓ 활성DG401CJ+ 개요
An analog switch is an integrated semiconductor device that routes a signal between circuit nodes under logic control. The DG401CJ+ belongs to the analog-switch and multiplexer category, where it sits above discrete MOSFET switches and below more complex multiplexing or switching systems. Each of its two channels can connect or disconnect one signal path, making the device suitable for sample-and-hold systems, test equipment, audio routing, and data-acquisition front ends.
Key electrical characteristics include a 45 Ω maximum on resistance and a 20 Ω typical value in the redesigned DG401 series. The manufacturer also specifies guaranteed on-resistance matching of 2 Ω maximum between switches and on-resistance flatness of 3 Ω maximum across the signal range. Charge injection is limited to 15 pC maximum, helping reduce switching glitches in precision measurement systems.
The DG401 series uses a CMOS-style analog-switch architecture that operates equally well in either signal direction. Two separately controlled switches provide independent routing for dual-channel or differential systems. The 75 ns switching-time figure published for the DG401 series supports high-speed sampling and measurement applications where the switch must settle rapidly after a control transition.
Typical uses include automated test equipment, sample-and-hold circuits, audio and video signal routing, analog measurement front ends, and instrumentation requiring two independently switched paths. The 16-pin PDIP package is suitable for through-hole prototyping, legacy industrial boards, and applications where a socketed or manually assembled package is preferred over a surface-mount option.
When designing around the DG401CJ+, treat the 45 Ω on resistance as part of the signal-path impedance budget and keep control-edge layout short to limit capacitive coupling. Because the device is a normally open switch, the signal path is disconnected until the corresponding logic input is asserted. Confirm the control polarity and timing against the manufacturer pin-description table before assigning PCB nets.
드롭인 대체품: DG401CJ+ — 동일 패키지, 핀 호환. PCB 재작업이 필요한 다른 패키지 부품은 제외됩니다.
이 시리즈의 변형
다음과 드롭인 호환되는 동일 시리즈 모델: DG401CJ+ (동일 폼 팩터 및 풋프린트) — 차이점: Charge Injection, Mounting Type, Package.
DG401CJ
✅ 드롭인 ⚠️ 사양 미검증📋 참조 대체품 (카탈로그에 없음)
DG401EJ+
✅ 드롭인 ⚠️ 사양 미검증📋 참조 대체품 (카탈로그에 없음)
DG401DJ+
✅ 드롭인 ⚠️ 사양 미검증가격 문의
데이터시트 보기 →DG401DJ
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
DG401CJ+ 최대 정격 & 전기적 특성
| Number of Switches | 2 circuits |
| Multiplexer Configuration | 1:1 |
| Switch Type | SPST (normally open) |
| On Resistance | 45 Ω maximum; 20 Ω typical |
| On-Resistance Matching Between Switches | 2 Ω maximum |
| On-Resistance Flatness | 3 Ω maximum |
| Charge Injection | 15 pC maximum |
| Switching Time | 75 ns |
| 동작 온도 범위 | Commercial grade |
| 패키지 | PDIP-16, 0.300 inch (7.62 mm) row spacing |
| 실장 유형 | Through hole |
| Data Sheet Revision | Rev. 2 |
| 수명 주기 상태 | Production |
DG401CJ+ pdip-16, 0.300 inch (7.62 mm) row spacing 핀 구성 가이드
DG401CJ+(pdip-16, 0.300 inch (7.62 mm) row spacing 패키지)의 핀 구성입니다. 핀 번호, 기능, 연결 다이어그램은 제조사 데이터시트에 정의되어 있습니다. 정확한 풋프린트와 솔더링 지침은 해당 문서를 참조하십시오.
다음에 대한 상세 핀아웃 데이터 없음: DG401CJ+.
다음을 참조하십시오: 데이터시트 전체 핀 구성은 다음을 참조하십시오.
일반적인 애플리케이션
DG401CJ+ 적합 용도: 6 애플리케이션s: Automated Test Equipment Signal Routing, Sample-and-Hold Acquisition Circuits, Audio and Video Signal Routing, Precision Instrumentation Front Ends, Dual-Channel Data Acquisition, Legacy Through-Hole Control Boards.
Automated Test Equipment Signal Routing
The DG401CJ+ is suited to automated test systems that must connect and isolate two measurement paths under sequencer control. Its two independent normally open channels allow a fixture to route a source, clamp, or return path without introducing additional crosstalk through a permanently closed switch. The 2 Ω maximum on-resistance matching and 3 Ω maximum flatness help keep the two paths electrically similar, while 75 ns switching time supports rapid test cycles. The 45 Ω maximum path resistance should be included in the source-impedance and accuracy budget when driving high-impedance detectors.
추천
Sample-and-Hold Acquisition Circuits
A sample-and-hold front end benefits from the DG401CJ+ because each SPST channel can disconnect the hold capacitor from the source between acquisitions. The normally open configuration prevents continuous loading of the input while the circuit is not sampling. With 15 pC maximum charge injection and a 75 ns switching time, the device supports acquisition circuits that require a defined settling interval and limited control-induced transient. Capacitor selection should still account for the injected charge, source impedance, leakage, and acquisition time.
추천
Audio and Video Signal Routing
The DG401CJ+ can route two low-frequency analog channels in audio, video, or communication equipment without introducing the broadband switching noise associated with mechanical relays. The 45 Ω maximum on resistance is manageable for many line-level or impedance-buffered paths, while guaranteed matching and flatness help maintain consistent channel behavior. The normally open switches remain isolated during idle periods. Use the manufacturer control-logic thresholds to interface directly with the supply levels used by the surrounding CMOS logic.
추천
Precision Instrumentation Front Ends
The DG401CJ+ is appropriate for instrumentation that selects or isolates signals entering a precision measurement chain. Matching of 2 Ω maximum and on-resistance flatness of 3 Ω maximum reduce channel-dependent gain errors when the source impedance is low relative to 45 Ω. The low 15 pC maximum charge injection also limits control-induced steps at the input of sensitive amplifiers. For very high-impedance sources, verify leakage and off-state behavior against the complete operating-temperature range before finalizing the design.
추천
Dual-Channel Data Acquisition
Two independent DG401CJ+ channels can support dual or differential acquisition when each switch is driven in the required sequence. The matched 45 Ω maximum on resistance helps preserve channel balance, and the 3 Ω maximum flatness specification limits signal-dependent resistance changes across the operating range. The device can also isolate an input during conversion to reduce interference between measurements. Sequencing the controls with the converter avoids overlapping acquisition and conversion periods and limits transient settling time at the input.
추천
Legacy Through-Hole Control Boards
The 16-pin PDIP package makes the DG401CJ+ practical for legacy through-hole control boards, prototype fixtures, and manually assembled industrial interfaces that are not being converted to surface-mount assembly. Two SPST channels provide economical routing without requiring multiple single-switch packages. The through-hole form factor also eases inspection and rework during low-volume production. Because the package is not surface mount, mixed-technology boards need the appropriate plated-through-hole footprint and adequate spacing for axial or manual insertion.
추천
추천 제품 요약
엔지니어링 참조 데이터: DG401CJ+ — 비교, 설계 지침 및 규정 준수 정보.
선택 가이드
대체품과의 비교
| 파라미터 | 이 제품 | DG401CJ | DG401EJ+ | DG401DJ+ | DG401DJ |
|---|---|---|---|---|---|
| Brand | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Vishay Siliconix |
| Package | PDIP-16, through hole | PDIP-16, through hole | PDIP-16, through hole | PDIP-16, through hole | DIP-16, through hole |
| Number of Switches | 2 | 2 | 2 | 2 | 2 |
| Switch Configuration | Dual SPST, normally open | Dual SPST, normally open | Dual SPST, normally open | Dual SPST, normally open | Dual SPST |
| On Resistance | 45 Ω maximum; 20 Ω typical | 45 Ω class | 45 Ω class | 45 Ω class | 30 Ω |
| Switching Time | 75 ns | 75 ns | 75 ns | 75 ns | 75 ns |
주요 차별점
- Guaranteed channel matching and flatness (vs DG401DJ)
- Defined high-speed switching performance (vs DG401DJ)
- Dual normally open routing in a through-hole package (vs MAX301CPE+)
설계 노트
Treat the DG401CJ+ on resistance as part of the source impedance seen by the next stage. With a 45 Ω maximum path resistance, a high-gain amplifier can produce an input-referred error proportional to that resistance. Use the guaranteed 2 Ω maximum matching and 3 Ω maximum flatness figures when budgeting channel-to-channel gain error, and avoid driving the switch from a source whose impedance is too high for the intended measurement accuracy.
Do not substitute the SOIC-16 DG401DY+T without redesigning the PCB because it uses a surface-mount package rather than the DIP-16 footprint of the DG401CJ+. In addition, a comparator listing a similar function is not necessarily pin-compatible. Confirm the two signal pins, common terminals, control inputs, and logic polarity against the manufacturer pin-description table before releasing a replacement to production.
Keep the control traces short and route them away from sensitive analog inputs to reduce capacitive injection from the switching edges. Place the device close to the source and destination nodes so the 45 Ω maximum on resistance does not add appreciable trace resistance or inductance. Use a ground reference plane and decouple the device's supply pins according to the manufacturer application circuit, following the data sheet's recommended values.
The control inputs and supply pins determine the device's electrical operating limits, but those detailed limits are not stated on the product page. Before applying power, verify the supply range, input logic thresholds, absolute maximum ratings, and signal-node voltage limits in the Analog Devices DG401 data sheet. Do not infer these ratings from the 45 Ω on resistance or from a distributor category description.
규정 준수 정보
A distributor listing associates the DG401CJ+ with RoHS, but it does not state a compliance status. The + suffix is associated with the manufacturer's lead-free ordering convention, while detailed declarations require confirmation from the manufacturer product documentation.
