DS90C363BMTX - 3.3V 18-Bit FPD-Link LVDS Transmitter | TI
부품 번호: DS90C363BMTX ✓ 활성| 수량 | 단가 | 합계 |
|---|---|---|
| 1 | $3.85 | $3.85 |
| 10 | $3.42 | $34.20 |
| 100 | $2.96 | $296.00 |
| 500 | $2.55 | $1,275.00 |
| 1,000 | $2.18 | $2,180.00 |
DS90C363BMTX 개요
A Flat Panel Display Link (FPD-Link) transmitter is a serializer IC that converts wide parallel CMOS/TTL buses (such as RGB video, control signals, and synchronization data) into a small number of high-speed differential LVDS pairs for transmission over a flexible flat cable or PCB trace to a remote display. FPD-Link sits within the hierarchy: serializer/deserializer (SerDes) -> LVDS interface -> display interface IC -> power management IC -> semiconductor. This category enables long-distance, low-EMI video distribution in space-constrained notebooks, monitors, and industrial displays.
Key specifications include 345 mV typical LVDS swing, compatibility with the TIA/EIA-644 LVDS standard, integrated PLL requiring no external components, narrow bus that reduces cable size and cost, transmit power-down mode consuming less than 37 uW (typical), and 40 percent less power dissipation than BiCMOS alternatives. The DS90C363B supports VGA, SVGA, XGA and dual-pixel SXGA, with programmable clock edge and selectable data mapping.
The device uses an internal PLL to multiply the input clock up to the required LVDS line rate, then performs 7:1 serialization per LVDS data channel using an LVDS current-mode driver. This minimizes pin count on the system side and dramatically reduces EMI compared with wide parallel TTL buses, making it ideal for notebook LCD panels, automotive instrument clusters, and industrial HMI displays.
Typical applications include notebook computer LCD panels, flat panel monitors, industrial HMI displays, automotive infotainment screens, and digital signage. The narrow LVDS bus significantly reduces cable and connector cost versus traditional TTL routing.
When designing with the DS90C363B, pay close attention to controlled-impedance routing of the four LVDS data pairs plus the LVDS clock pair; use 100 ohm differential impedance and keep skew tight to preserve data and clock alignment at the receiver.
This page synthesizes distributor pricing, drop-in alternatives, application notes, and practical PCB layout guidance not aggregated on any single distributor or manufacturer page.
드롭인 대체품: DS90C363BMTX — 동일 패키지, 핀 호환. PCB 재작업이 필요한 다른 패키지 부품은 제외됩니다.
빠른 비교 도구 — 나란히 비교할 대체 부품을 선택하십시오:
DS90C363BMTX/NOPB
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
DS90C365AMTX/NOPB
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
DS90C363BMTX
✅ 드롭인✓ 재고 있음
$2.18 / 개
데이터시트 보기 →DS90CF363AMTDX
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
DS90C363AMTX
✅ 드롭인 ⚠️ 사양 미검증📋 참조 대체품 (카탈로그에 없음)
DS90C363BMTX 사양
| 기능 | LVDS Transmitter (FPD-Link Serializer) |
| 공급 전압 | 3.3 V (typ.) |
| Input Data Width | 18-bit parallel RGB |
| 최대 클록 주파수 | 65 MHz |
| Throughput | Up to 1.3 Gbps |
| Bandwidth | Up to 170 Megabytes/sec |
| LVDS Swing | 345 mV (typ.) |
| Number of LVDS Data Pairs | 4 data + 1 clock |
| LVDS Standard | TIA/EIA-644 |
| PLL | Integrated, no external components |
| Tx Power-down Current | <37 uW (typ.) |
| 패키지 | 48-TSSOP (MTD) |
| 실장 유형 | Surface Mount |
| RoHS 상태 | Compliant |
| Lead-Free | Yes |
DS90C363BMTX 48-tssop (mtd) 핀 구성 가이드
DS90C363BMTX(48-tssop (mtd) 패키지)의 핀 구성입니다. 핀 번호, 기능, 연결 다이어그램은 제조사 데이터시트에 정의되어 있습니다. 정확한 풋프린트와 솔더링 지침은 해당 문서를 참조하십시오.
다음에 대한 상세 핀아웃 데이터 없음: DS90C363BMTX.
다음을 참조하십시오: 데이터시트 전체 핀 구성은 다음을 참조하십시오.
일반적인 애플리케이션
DS90C363BMTX 적합 용도: 6 애플리케이션s: Notebook Computer LCD Panels, Flat Panel Monitor, Industrial HMI Displays, Automotive Infotainment Displays, Digital Signage and Kiosk Displays, Medical Imaging Displays.
Notebook Computer LCD Panels
The DS90C363BMTX is purpose-built for notebook LCD panels where the wide parallel RGB bus must be converted to a narrow LVDS cable that crosses the hinge between the motherboard and the lid. Its 65 MHz clock rate covers XGA panels at 60 Hz refresh, and the integrated PLL removes the boundary layer and external loop filter required by older discrete FPD-Link designs. The 345 mV LVDS swing and TIA/EIA-644 compliance guarantee interoperability with panel-side TIA/EIA-644 receivers from TI, Parade, and Novatek. Designers pair it with a compatible LVDS receiver such as the DS90CF364 on the panel side, then route the four LVDS data pairs plus clock pair as 100 ohm differential pairs across the hinge cable with controlled skew.
추천
Flat Panel Monitor
External LCD monitors from 15-inch XGA through 20-inch SXGA commonly use the DS90C363BMTX to transport RGB video from the controller board to the panel T-con over a short LVDS cable. Its 1.3 Gbps aggregate throughput supports XGA at 60 Hz with comfortable timing margin, and the power-down current of less than 37 uW enables aggressive panel sleep states that extend monitor standby power ratings. Compared with parallel TTL routing, the four-data-pair LVDS link reduces connector pin count by 5x, allowing slimmer monitor bezels and lower-cost cable assemblies. TI's reference schematics show typical usage with a separate LVDS receiver on the panel T-con board, an I2C-controlled scalar IC, and a backlight driver.
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Industrial HMI Displays
Factory-floor HMI panels benefit from VGA displays that are designed to operate reliably in electrically noisy environments near motor drives and switched-mode power supplies. The DS90C363BMTX's LVDS signaling inherently rejects common-mode noise on the cable, and the low 345 mV swing minimizes radiated EMI that could interfere with adjacent industrial sensors. The integrated PLL eliminates sensitive external loop-filter components that could drift in industrial temperature ranges, simplifying long-term reliability. Engineers typically pair the DS90C363BMTX with a ruggedized LVDS receiver on the panel side and route the four data pairs plus clock pair as tightly skew-matched differential pairs across a shielded industrial-grade cable.
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Automotive Infotainment Displays
In-vehicle infotainment (IVI) head units with central displays use the DS90C363BMTX to bridge the head-unit main PCB and the remote display module across the dashboard. The 65 MHz clock rate covers typical 7-inch to 9-inch WVGA panels running at 60 Hz, while the low 37 uC Tx-power-down current enables deep sleep modes that reduce parasitic battery drain when the vehicle is parked. The narrow LVDS cable simplifies dashboard harness design and reduces weight versus parallel TTL cabling. Automotive-grade variants such as the DS90C363BMTX-Q1 (where available) extend the operating temperature range and add AEC-Q100 qualification for under-hood or dashboard deployments.
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Digital Signage and Kiosk Displays
Digital signage panels in retail, transit, and kiosk deployments require long cable distances between the media player and the display panel, often across articulated mounts or kiosk frames. The DS90C363BMTX drives LVDS across these distances with robust signal integrity thanks to its differential LVDS pairs and low EMI, supporting panel sizes from 10-inch to 19-inch at XGA resolution. Its integrated PLL and lack of external loop-filter components reduce BOM and assembly cost, which is critical for price-sensitive signage rollouts. The DS90C365A upgrade option provides additional clock headroom for higher-resolution signage without any PCB layout changes.
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Medical Imaging Displays
Diagnostic and patient-monitoring displays in medical equipment benefit from the DS90C363BMTX's clean LVDS signaling and predictable EMI behavior, both critical for medical EMC standards like IEC 60601-1-2. The 65 MHz clock covers typical 1280x1024 SXGA medical panels at reduced blanking, while the low power dissipation keeps thermal rise within the patient-adjacent enclosure limits. The integrated PLL simplifies the BOM, easing the regulatory documentation burden for medical device submissions. Designers typically combine the DS90C363BMTX with a medical-grade LVDS receiver on the panel side and route the four LVDS data pairs plus clock as controlled-impedance pairs across the medical-grade display cable assembly.
추천
추천 제품 요약
엔지니어링 참조 데이터: DS90C363BMTX — 비교, 설계 지침 및 규정 준수 정보.
선택 가이드
대체품과의 비교
| 파라미터 | 이 제품 | DS90C363BMTX/NOPB | DS90C365AMTX/NOPB | DS90C363BMTX | DS90CF363AMTDX | DS90C363AMTX |
|---|---|---|---|---|---|---|
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | National Semiconductor | Rochester Electronics | Texas Instruments |
| Package | 48-TSSOP (MTD) | 48-TSSOP (MTD) - same | 48-TSSOP (MTD) - same | 48-TSSOP (MTD) - same | 48-TSSOP (MTD) - same | 48-TSSOP (MTD) - same |
| Maximum Clock Frequency | 65 MHz | 65 MHz | 87 MHz | 65 MHz | 65 MHz | 65 MHz |
| Throughput | 1.3 Gbps | 1.3 Gbps | 1.74 Gbps | 1.3 Gbps | 1.3 Gbps | 1.3 Gbps |
| LVDS Standard | TIA/EIA-644 | TIA/EIA-644 | TIA/EIA-644 | TIA/EIA-644 | TIA/EIA-644 | TIA/EIA-644 |
| Integrated PLL | Yes | Yes | Yes | Yes | Yes | Yes |
| RoHS / Lead-Free | Yes (MTX = standard, NOPB = lead-free) | Yes / lead-free | Yes / lead-free | Yes (legacy) | Yes (legacy) | Yes (legacy) |
주요 차별점
- Pin-compatible 87 MHz upgrade path available (vs DS90C365AMTX/NOPB)
- Integrated PLL requires no external loop filter (vs DS90C363AMTX (A-revision))
- TIA/EIA-644 LVDS standard compliance (vs Proprietary LVDS transceivers)
설계 노트
Route the four LVDS data pairs plus the LVDS clock pair as 100 ohm differential microstrip or stripline, keeping intra-pair length matching tight (target < 5 mil mismatch). Per TI's FPD-Link layout guidelines, keep the LVDS pairs away from switching power supply nodes and TTL bus edges to minimize crosstalk. Place the LVDS 100 ohm termination resistor at the far end of each pair, near the panel-side connector, and keep ground pours continuous under the entire LVDS routing region to maintain a controlled impedance reference.
Decouple the +3.3V supply pin with a 0.1 uF ceramic capacitor placed within 3 mm of the supply pin, and add a 10 uF bulk capacitor on the same net. Estimated local decoupling supports the DS90C363B's typical 1.3 Gbps operation; insufficient decoupling can manifest as PLL jitter and intermittent display artifacts. Per TI's application notes, the PLL analog supply pin (if separate) should be filtered with a ferrite bead and additional 0.1 uF capacitor.
Estimate inter-pair skew at the receiver: for a 1 m FR4 LVDS cable at 1.3 Gbps, dielectric dispersion contributes roughly 30-50 ps of skew between data and clock pairs. Match trace lengths to within 150 mil of each other to keep the receiver's internal deskew window happy. If the cable length exceeds 500 mm, consider periodic LVDS re-driver stages or switching to DS90C365A family for higher skew tolerance.
Do not leave the PWRDN pin floating; tie it high (enabled) or low (powered down) through a 10 kohm pull-up or pull-down resistor. Failing to do so can leave the device in a metastable state at power-up, causing the panel to show random garbage instead of valid video. Also avoid routing TTL RGB data lines under the LVDS output pairs, and never share the LVDS 100 ohm termination resistor between two LVDS pairs.
규정 준수 정보
DS90C363BMTX/NOPB variant is lead-free and RoHS compliant per TI product page and DigiKey listing. Standard DS90C363BMTX (without NOPB suffix) is also RoHS compliant but is the legacy non-automotive-grade version. AEC-Q100 not applicable unless using the automotive Q1 suffix variant.
