DS90C365MTD - 85MHz FPD-Link LVDS Transmitter | Texas Instruments
부품 번호: DS90C365MTD ✗ 단종DS90C365MTD 개요
An LVDS transmitter is a high-speed differential interface driver that converts low-voltage CMOS/TTL logic into a low-EMI differential signal. LVDS belongs to the differential line-driver family and the broader interface-IC hierarchy, providing a practical alternative to parallel bus links when cable distance, signal count, EMI control, or data rate makes parallel routing impractical.
The device's principal features include a 345 mV typical LVDS output swing, operation from a single 3 V to 3.6 V supply, and an internal PLL that requires no external components. The source also identifies compatibility with the TIA/EIA-644 LVDS standard. These characteristics make the transmitter useful where high data throughput must be transferred through a reduced-size differential link.
The programmable architecture supports both 18-bit and 24-bit FPD-Link configurations while operating as a transmitter rather than a bidirectional transceiver. Its differential output is intended to reduce conducted emissions and radiated EMI by limiting common-mode voltage excursions. The internal PLL simplifies implementation compared with transmitter designs that require external loop-filter components.
Typical uses include flat-panel display links, digital video interfaces, industrial display controllers, and embedded display systems that transmit wide parallel data over a compact cable. In a practical design, the parallel data enters the transmitter, the internal serializer converts it into a high-speed differential stream, and a matched LVDS receiver reconstructs the data at the display endpoint.
Designers should use controlled-impedance differential routing, maintain the receiver and transmitter ground reference appropriately, and verify connector and cable compatibility with the LVDS standard. Supply decoupling should be placed close to the device, while signal-integrity evaluation should include the complete transmitter-to-receiver channel rather than relying only on simulation of the IC.
This page combines verified distributor information, interface specifications, application guidance, and drop-in replacement analysis. It distinguishes electrically similar interface ICs from true pin-compatible alternatives and highlights where a PCB redesign is still required.
드롭인 대체품: DS90C365MTD — 동일 패키지, 핀 호환. PCB 재작업이 필요한 다른 패키지 부품은 제외됩니다.
DS90C365AMT/NOPB
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
DS90C365MTD 사양
| Device Type | LVDS transmitter |
| Number of Drivers | 1 driver |
| Number of Receivers | 0 receivers |
| Supply Voltage Range | 3 V to 3.6 V |
| Protocol | FPD-Link, LVDS |
| Data Format | 18-bit or 24-bit Flat Panel Display Link |
| Pixel Clock | 85 MHz |
| Maximum Throughput | 2.38 Gbps |
| Maximum Bandwidth | 297.5 MB/s |
| LVDS Output Swing | 345 mV typical |
| PLL Requirement | No external components required |
| LVDS Standard Compatibility | TIA/EIA-644 |
| 패키지 | 48-lead TSSOP |
| Package Width | 6.10 mm |
| Lead Pitch | 0.240 mm |
| Packaging | Tube |
DS90C365MTD 6.10 mm 핀 구성 가이드
DS90C365MTD(6.10 mm 패키지)의 핀 구성입니다. 핀 번호, 기능, 연결 다이어그램은 제조사 데이터시트에 정의되어 있습니다. 정확한 풋프린트와 솔더링 지침은 해당 문서를 참조하십시오.
다음에 대한 상세 핀아웃 데이터 없음: DS90C365MTD.
다음을 참조하십시오: 데이터시트 전체 핀 구성은 다음을 참조하십시오.
일반적인 애플리케이션
DS90C365MTD 적합 용도: 6 애플리케이션s: Flat-Panel Display Links, Industrial Display Controllers, Digital Video Interfaces, Embedded Display Systems, Low-EMI Data Transmission, High-Speed Point-to-Point Links.
Flat-Panel Display Links
The DS90C365MTD is intended for 18-bit or 24-bit Flat Panel Display Link-85 systems that transfer display data over a compact differential connection. Its verified 85 MHz pixel-clock capability and up-to-2.38 Gbps throughput suit parallel-to-serial display transmission where reducing cable pin count and EMI are important. The transmitter can sit beside a display controller and drive a twisted-pair LVDS cable, but the receiver, cable, and connector must support the intended data rate. Differential routing and return-path continuity remain as important as clock throughput because an unsuitable channel can prevent reliable recovery even when the transmitter itself operates within specification.
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Industrial Display Controllers
The DS90C365MTD fits industrial display-controller boards that need to move wide display payloads across a narrow differential interface. Its programmable support for 18-bit and 24-bit FPD-Link formats gives designers flexibility when matching different panel timing, while the 345 mV typical LVDS swing is designed to reduce signal amplitude and electromagnetic interference. In an industrial enclosure, this can simplify cable routing and reduce susceptibility to common-mode interference relative to a wide parallel bus. The implementation must still account for grounding, connector return paths, and the receiver's electrical and timing requirements.
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Digital Video Interfaces
The DS90C365MTD can be used in digital-video equipment that already uses FPD-Link signaling and requires a dedicated transmit-only device. Its up-to-297.5 MB/s verified bandwidth and 18-bit or 24-bit payload support provide a defined interface for carrying display information between a controller and an endpoint. Compared with exposing a 24-bit parallel bus externally, a differential link reduces signal count and can improve EMI behavior. It is most appropriate when the downstream receiver is explicitly compatible with FPD-Link; a generic LVDS receiver may not interpret the serialized data or support the required framing.
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Embedded Display Systems
Embedded control systems with compact LCD or TFT panels can use the DS90C365MTD to move display data from a host or graphics engine to a remote display assembly. The 48-lead TSSOP package provides a PCB footprint suitable for compact industrial-control electronics, while the single-driver topology keeps the transmitter focused on one outbound differential channel. The verified 3 V to 3.6 V operating range also aligns with many compact 3.3 V systems, subject to each rail's noise and tolerance requirements. Designers should validate the complete display timing, LVDS receiver, cable length, and connector arrangement rather than relying on data rate alone.
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Low-EMI Data Transmission
The DS90C365MTD is appropriate when a design needs high-speed data transfer with lower electromagnetic emissions than a parallel bus. Its differential LVDS output has a verified 345 mV typical swing, and the architecture reduces the number of conductors required for an 18-bit or 24-bit payload. That combination can improve cable practicality and simplify routing across equipment boundaries. The real-world benefit depends on an implemented controlled-impedance differential channel, common-mode control, and correct receiver termination; a poor cable or ground arrangement can undermine the low-EMI benefit.
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High-Speed Point-to-Point Links
The DS90C365MTD can support point-to-point equipment links when the transmitter and receiver are intentionally configured around FPD-Link framing. Verified throughput of up to 2.38 Gbps provides substantial link capacity, while the internal PLL eliminates the need for external loop-filter components. This is useful in rack-mounted, test-equipment, or industrial-control systems where a wide parallel bus would require many signal traces or connector pins. The implementation should verify receiver clock tolerance, cable attenuation, connector insertion loss, and signal-integrity margins across the required data rate and environmental conditions.
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추천 제품 요약
엔지니어링 참조 데이터: DS90C365MTD — 비교, 설계 지침 및 규정 준수 정보.
선택 가이드
대체품과의 비교
| 파라미터 | 이 제품 | DS90C365AMT/NOPB |
|---|---|---|
| Brand | National Semiconductor | Texas Instruments |
| Package | 48-lead TSSOP | 48-lead TSSOP - same package |
| Device Type | LVDS transmitter | FPD-Link LVDS transmitter |
| Supported Data Width | 18-bit or 24-bit FPD-Link | 18-bit or 24-bit FPD-Link |
주요 차별점
- Dedicated single-driver FPD-Link architecture (vs SN65LVDS95DGG)
- Same-package family replacement path (vs DS90C365AMT/NOPB)
- High serial throughput from a narrow bus (vs SN65LVDS95DGG)
설계 노트
Route the differential LVDS pair as a controlled-impedance transmission line with closely matched spacing, uninterrupted reference plane, and minimized stubs. Avoid routing the pair across plane splits or through unrelated noisy circuitry. Keep the connector, cable, and receiver termination within the validated channel configuration because transmitter timing specifications alone do not guarantee system-level signal integrity.
Place the device's supply-decoupling network close to its power and ground pins and connect it through the shortest practical path. The verified operating range is 3 V to 3.6 V, so verify ripple, transient excursions, and sequencing at every system operating state. The exact recommended capacitor values and stability requirements were not present in the supplied excerpts and should be taken from the manufacturer datasheet.
Treat the transmitter, receiver, connectors, and cable as one complete 85 MHz FPD-Link channel. Check differential voltage, common-mode behavior, receiver threshold margins, jitter, and cable loss rather than validating only at the IC pins. The verified 2.38 Gbps throughput and 345 mV typical swing describe the transmitter capability, but they do not remove channel-dependent failure modes.
Do not substitute a similarly packaged generic LVDS driver without verifying its complete pin map and protocol. The SN65LVDS95DGG appears in the comparison data as a three-output device rather than the DS90C365MTD's one-driver transmitter. Package count alone does not establish pin compatibility, so use the single verified same-family alternative or perform a documented board redesign.
규정 준수 정보
The verified excerpts do not provide explicit RoHS, REACH, lead-free, halogen-free, or conflict-minerals statements. AEC-Q100 is treated as not applicable because the verified descriptions identify an industrial display interface rather than an automotive-qualified device; confirm all environmental and regulatory requirements with the manufacturer.
