DS90C387VJD-TI - Dual Pixel LVDS Transmitter | Texas Instruments
부품 번호: DS90C387VJD-TI ✓ 활성DS90C387VJD-TI 개요
A dual-pixel LVDS display interface, also called LDI, is a high-speed serial display-link technology that reduces the number of parallel signal traces required between a graphics host and a display panel. The DS90C387VJD-TI accepts parallel CMOS/TTL pixel data and converts it into low-voltage differential signaling, while the paired receiver reconstructs the data at the display end. This hierarchy places the device within interface ICs, display-interface transceivers, LVDS signaling, and semiconductor interface components.
The principal feature set includes 48-bit dual-pixel input, eight LVDS output streams, support for SVGA and QXGA resolutions, and +3.3 V operation. The transmitter is intended for systems in which a display controller cannot directly drive the long, high-speed differential bus required between the host and flat-panel display. Its differential outputs are designed to support reliable transfer of pixel data across a cable or PCB connection while reducing signal-noise pickup relative to a single-ended interface.
The DS90C387VJD-TI is a display transmitter rather than a general-purpose LVDS transceiver, and its clocking, data mapping, control-signal timing, and receiver pairing must be treated as a coordinated system. The 100-pin TQFP package provides the numerous data, control, power, and ground connections required by the dual-pixel architecture. Its surface-mount construction supports automated board assembly, while the dense pin count requires careful escape routing and controlled-length routing between the host and display interface.
Typical applications include desktop flat-panel monitors, industrial HMI panels, medical display controllers, automotive display links, and other SVGA or QXGA systems that use the DS90C387 and DS90CF388 transmitter/receiver pairing. The interface is especially appropriate where a parallel host bus must be converted to a compact differential display connection across a larger physical distance.
Designers should use the pin-description table and recommended decoupling arrangement in the Texas Instruments datasheet when assigning every signal and planning the power network. Differential LVDS pairs should be routed as tightly coupled pairs with controlled impedance, while the CMOS/TTL inputs require clean return paths and adequate settling time. Board-level validation should include power-up sequencing, blanking-period control signaling, data mapping, receiver synchronization, and compliance with the display timing requirements of the final panel system.
This page combines the manufacturer product information with a practical view of system compatibility, package constraints, and display-link implementation considerations. It also distinguishes exact drop-in alternatives from family members that require different packages or interface functions, helping engineers avoid treating electrically similar LVDS devices as PCB-compatible replacements.
드롭인 대체품: DS90C387VJD-TI — 동일 패키지, 핀 호환. PCB 재작업이 필요한 다른 패키지 부품은 제외됩니다.
DS90C387VJDX/NOPB
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
DS90C387AVJD
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
DS90C387VJD/NOPB
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
DS90C387VHG
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
DS90C388
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
DS90C387VJD-TI 사양
| Product Type | Dual Pixel LVDS Display Interface Transmitter |
| 공급 전압 | +3.3 V |
| Supported Resolution | SVGA to QXGA |
| CMOS/TTL Input Width | 48 bits |
| LVDS Output Stream Count | 8 streams |
| Pixel Data Format | Dual Pixel 24-bit color |
| Transmitted Control Signals | VSYNC, HSYNC, DE, and 2 user-defined signals |
| Differential Signaling Standard | LVDS (Low Voltage Differential Signaling) |
| Receiver Pairing | DS90CF388 |
| 패키지 | 100-pin TQFP, 14 mm x 14 mm |
| 실장 유형 | Surface Mount |
| 카테고리 | Interface ICs |
| 기능 | Parallel CMOS/TTL-to-LVDS transmitter |
| Host-to-Display Architecture | Dual Pixel LDI |
| Control Signal Transmission | During blanking |
DS90C387VJD-TI 100-pin tqfp, 14 mm x 14 mm 핀 구성 가이드
DS90C387VJD-TI(100-pin tqfp, 14 mm x 14 mm 패키지)의 핀 구성입니다. 핀 번호, 기능, 연결 다이어그램은 제조사 데이터시트에 정의되어 있습니다. 정확한 풋프린트와 솔더링 지침은 해당 문서를 참조하십시오.
다음에 대한 상세 핀아웃 데이터 없음: DS90C387VJD-TI.
다음을 참조하십시오: 데이터시트 전체 핀 구성은 다음을 참조하십시오.
일반적인 애플리케이션
DS90C387VJD-TI 적합 용도: 6 애플리케이션s: Desktop Flat-Panel Monitor, Industrial Human-Machine Interface, Medical Display Controller, Automotive Display Link, Instrument Panel and Test Equipment, Video Capture and Processing System.
Desktop Flat-Panel Monitor
DS90C387VJD-TI fits a desktop monitor architecture that converts 48 bits of parallel CMOS/TTL dual-pixel color data into 8 LVDS streams. That interface allows the graphics source to communicate with a panel over differential conductors designed for a physical separation between host and display electronics. The architecture supports SVGA through QXGA resolutions and carries VSYNC, HSYNC, DE, and two user-defined signals during blanking. The paired DS90CF388 should be used when implementing the complete link, and panel timing, cable length, and pixel-clock requirements must be validated together.
추천
Industrial Human-Machine Interface
The DS90C387VJD-TI can form the host-side link in an industrial HMI when the panel implements a compatible dual-pixel SVGA/QXGA LVDS interface. Its 48-bit CMOS/TTL input and 8 differential outputs reduce the number of parallel high-speed traces crossing the board or cable assembly, while blanking-period control signaling preserves synchronization information. For industrial deployment, confirm the exact temperature grade, isolation strategy, grounding method, and EMC performance. A Request a Quote can confirm the currently orderable suffix and production availability.
추천
Medical Display Controller
DS90C387VJD-TI is applicable to a medical display controller that uses the established DS90C387/DS90CF388 dual-pixel interface rather than a proprietary panel link. The transmitter accepts parallel CMOS/TTL pixels and sends them as 8 LVDS streams, supporting SVGA through QXGA while carrying synchronization and data-enable information during blanking. Differential transmission can help reduce noise pickup over panel interconnects, but it does not replace medical-system validation. Review the complete electrical timing, isolation, grounding, and applicable medical qualification requirements before releasing the design.
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Automotive Display Link
DS90C387VJD-TI can be evaluated for an automotive display link when the vehicle platform uses a compatible +3.3 V dual-pixel LVDS topology and the DS90CF388 receiver. Eight LVDS streams carry 48-bit color information, and VSYNC, HSYNC, DE, and user-defined controls travel during blanking. Automotive use requires careful review of temperature grade, electromagnetic compatibility, transient immunity, connector and cable behavior, and supplier change control. The available evidence establishes display-interface functionality but does not establish AEC-Q100 qualification for this exact ordering code.
추천
Instrument Panel and Test Equipment
DS90C387VJD-TI suits instrument and test-equipment panels that accept a host-generated dual-pixel display stream. The parallel input interface allows the transmitter to sit between a display controller and the external panel, while the 8 LVDS outputs provide a more noise-resistant differential connection across the instrument chassis. The design must support the selected panel's SVGA or QXGA timing, including valid blanking periods for embedded control signals. Cable qualification, impedance control, and receiver synchronization testing are essential when the display assembly is remote from the main instrument electronics.
추천
Video Capture and Processing System
DS90C387VJD-TI can serve as the final parallel-to-LVDS stage in a display or processing system that generates dual-pixel CMOS/TTL video data. Converting 48 bits into 8 LVDS streams simplifies the external display connection and supports QXGA-class panel timing. The transmitter is most appropriate when the receiving panel or downstream board is explicitly designed for the DS90CF388 ecosystem; otherwise, a different serializer must be selected because generic LVDS transmitters may use incompatible lane rates, clocking, or data mapping. Verify blanking-time control-signal behavior at the target refresh rate.
추천
추천 제품 요약
엔지니어링 참조 데이터: DS90C387VJD-TI — 비교, 설계 지침 및 규정 준수 정보.
선택 가이드
대체품과의 비교
| 파라미터 | 이 제품 | DS90C387VJDX/NOPB | DS90C387AVJD | DS90C387VJD/NOPB | DS90C387VHG | DS90C388 |
|---|---|---|---|---|---|---|
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments |
| Package | 100-pin TQFP, 14 mm x 14 mm | 100-pin TQFP, 14 mm x 14 mm | 100-pin TQFP | 100-pin TQFP | 100-pin TQFP | 100-pin TQFP |
| Device Family | DS90C387 | DS90C387 | DS90C387 | DS90C387 | DS90C387 | DS90C388 |
| Pin Count | 100 pins | 100 pins | 100 pins | 100 pins | 100 pins | 100 pins |
주요 차별점
- Direct manufacturer-family replacement with complete terminal compatibility (vs DS90C387VJDX/NOPB)
- Dedicated 48-bit dual-pixel input architecture (vs DS90C388)
- Same 100-pin TQFP PCB footprint across the primary family options (vs DS90C387AVJD)
설계 노트
Treat every DS90C387VJD-TI LVDS output as a coupled differential pair and route it over a continuous ground reference plane. Match the trace geometry to the PCB stack-up and connector or cable impedance, keep the two conductors of a pair at approximately equal length, and avoid discontinuities beneath the pair. Because the device is packaged in a 100-pin TQFP, plan the fan-out carefully so other high-speed or switching nets do not pass between coupled LVDS traces.
Use the Texas Instruments datasheet's recommended bypass capacitors and placement directly at the transmitter's supply and ground pins. Separate the +3.3 V display-interface rail from noisy switching-converter nodes, and keep return current continuous beneath the package. Validate the rail with an oscilloscope at the device under the highest expected pixel-clock and data activity; logic-level correctness alone does not establish adequate power or return-path integrity for a multi-lane LVDS transmitter.
Do not substitute a generic 8-channel LVDS driver solely because its lane count matches. DS90C387VJD-TI uses a defined 48-bit dual-pixel data mapping, transmits VSYNC, HSYNC, DE, and two user-defined signals during blanking, and belongs to a coordinated transmitter/receiver design. Verify clock relationships, lane polarity, control-signal timing, and panel acceptance with the DS90CF388 receiver and the target display timing before approving a substitute.
Validate the completed interface with the intended panel and cable rather than only at the transmitter output. Check differential eye quality, common-mode voltage, data timing relative to the forwarded clock, and control-signal behavior during blanking. ESD protection, connectors, and cable stubs can materially affect a high-speed display link, so include realistic cables, protection devices, and panel loading in the test setup and compare results against the manufacturer's timing and electrical limits.
규정 준수 정보
The verified manufacturer excerpt does not explicitly state compliance or qualification for the exact DS90C387VJD-TI ordering code. Check the current Texas Instruments product page and ordering information before making a compliance declaration.
