EP2AGX190FF35I3G - Arria II GX FPGA 190K LE | Intel | Altera
부품 번호: EP2AGX190FF35I3G ⚠ 최종 구매| 수량 | 단가 | 합계 |
|---|---|---|
| 1 | $2850 | $2,850.00 |
| 10 | $2620 | $26,200.00 |
| 100 | $2310 | $231,000.00 |
| 500 | $2050 | $1,025,000.00 |
| 1,000 | $1840 | $1,840,000.00 |
EP2AGX190FF35I3G 개요
A Field-Programmable Gate Array (FPGA) is a semiconductor device built around an array of configurable logic blocks (CLBs), programmable routing, and embedded hard IP such as transceivers, block RAM, multipliers, and PLLs. Within the broader semiconductor taxonomy, an FPGA is a programmable logic device (PLD), which sits under the umbrella of digital integrated circuits (ICs) and, more specifically, application-specific standard products for parallel hardware acceleration. FPGAs are reprogrammed at the bitstream level, giving them ASIC-like performance with NRE cost near zero, making them the workhorse of prototyping, low-volume production, and reconfigurable computing.
The EP2AGX190FF35I3G is fabricated on a 40 nm low-power process, supports core voltages of 0.9 V with I/O banks configurable to 1.2 V to 3.3 V standards (LVDS, LVTTL, LVCMOS, HSTL, SSTL), and integrates 8 high-speed transceiver channels capable of multi-gigabit serial links. The part number suffix 'I3' denotes the industrial temperature grade (-40 °C to +100 °C junction) with speed grade 3, while the trailing 'G' indicates lead-free / RoHS-compliant lead finish.
The architecture combines a logic fabric of adaptive logic modules (ALMs), M9K block RAM tiles, MLAB distributed RAM, embedded 18x18 multipliers, and a hard PCI Express Gen1/Gen2 controller. The high-speed transceivers are backed by on-die signal-conditioning circuitry, supporting protocols such as PCIe, GigE, Serial RapidIO, and serial digital video (SDI/HD-SDI). The 'FF35' package designation refers to a 35 mm body flip-chip BGA with 1152 balls on a 1.0 mm pitch - an Altera-standard high-pin-count footprint shared across multiple Arria II GX density grades.
Typical applications include high-definition video broadcast and processing, wireless baseband DSP acceleration, military/aerospace signal intelligence (SIGINT) and radar preprocessing, telecom backplane bridging, medical imaging pipelines, and ASIC prototyping for ASIC-replacement designs. The combination of high logic density, embedded transceivers, and on-chip PCIe makes it well suited to data-path-heavy workloads.
When designing with this part, allocate sufficient PCB layers (>= 12) for the FCBGA breakout, follow Intel/Altera power-supply sequencing requirements, and use the Quartus II / Quartus Prime design toolchain for synthesis, place-and-route, and timing closure. The large 35x35 mm package mandates a high-performance PCB stack-up; thermal management relies on a heat spreader attached directly to the flip-chip lid rather than forced-air cooling alone.
This page synthesizes distributor pricing snapshots, drop-in alternative FPGAs from the same Arria II GX family, and practical design notes not found in the manufacturer datasheet alone, giving procurement and engineering teams a single, decision-ready reference.
드롭인 대체품: EP2AGX190FF35I3G — 동일 패키지, 핀 호환. PCB 재작업이 필요한 다른 패키지 부품은 제외됩니다.
이 시리즈의 변형
다음과 드롭인 호환되는 동일 시리즈 모델: EP2AGX190FF35I3G (동일 폼 팩터 및 풋프린트) — 차이점: Package, Speed Grade, Operating Temperature, Logic Elements, Mounting Type.
빠른 비교 도구 — 나란히 비교할 대체 부품을 선택하십시오:
EP2AGX190FF35I5G
✅ 드롭인✓ 재고 있음
$1350 / 개
데이터시트 보기 →EP2AGX190FF35C6G
✅ 드롭인✓ 재고 있음
$188 / 개
데이터시트 보기 →EP2AGX190FF35C5G
✅ 드롭인✓ 재고 있음
$1245 / 개
데이터시트 보기 →EP2AGX190FF35C4G
✅ 드롭인✓ 재고 있음
$2350 / 개
데이터시트 보기 →EP2AGX125FF35I5N
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
EP2AGX125FF35I5G
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
EP2AGX125FF35I3G
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
EP2AGX125EF35I5G
✅ 드롭인✓ 재고 있음
$1190 / 개
데이터시트 보기 →EP2AGX190FF35I3G 최대 정격 & 전기적 특성
| Family | Arria II GX |
| Logic Elements (LE) | 181,165 |
| User I/O Pins | 612 |
| Embedded Memory (bits) | 10,177,536 |
| Transceivers | 8 high-speed transceiver channels (multi-gigabit) |
| Core Voltage | 0.9 V |
| I/O Voltage Standards | 1.2 V to 3.3 V (LVTTL, LVCMOS, LVDS, HSTL, SSTL) |
| Process Node | 40 nm |
| 동작 온도 | -40 °C to +100 °C (industrial, suffix I) |
| Speed Grade | 3 |
| 패키지 | 1152-ball FC-FBGA (FF35), 35 mm body |
| 실장 유형 | Surface Mount (flip-chip BGA) |
| RoHS 상태 | Compliant (suffix G) |
| Lead-Free | Yes |
| Programming Toolchain | Quartus II / Quartus Prime |
EP2AGX190FF35I3G 핀 구성
| 핀 1 | VCC — Power supply (general I/O bank) |
| 핀 2 | IO_BANK_A[0] — User I/O - Bank A |
| 핀 3 | GND — Ground reference |
| 핀 4 | GXB_TX[0]_p — Transceiver channel 0 TX positive (high-speed serial) |
| 핀 5 | GXB_TX[0]_n — Transceiver channel 0 TX negative |
| 핀 6 | GXB_RX[0]_p — Transceiver channel 0 RX positive |
| 핀 7 | GXB_RX[0]_n — Transceiver channel 0 RX negative |
| 핀 8 | VCCL_GXB — Transceiver analog supply |
| 핀 9 | VCCA_PLL — PLL analog supply |
| 핀 10 | nCONFIG — Configuration reset (active low) |
| 핀 11 | nSTATUS — Configuration status (active low) |
| 핀 12 | CONF_DONE — Configuration complete (open drain) |
| 핀 13 | MSEL[0] — Configuration mode select |
| 핀 14 | MSEL[1] — Configuration mode select |
| 핀 15 | TCK — JTAG clock |
| 핀 16 | TMS — JTAG mode select |
| 핀 17 | TDI — JTAG data in |
| 핀 18 | TDO — JTAG data out |
| 핀 19 | CLK[0]_p — Differential clock input 0 positive |
| 핀 20 | CLK[0]_n — Differential clock input 0 negative |
| 핀 21 | VCC_CORE — Core voltage (0.9 V) |
| 핀 22 | GND — Ground reference |
| 핀 23 | VCCIO[0] — I/O bank 0 reference voltage |
| 핀 24 | IO[0] — User I/O pin |
일반적인 애플리케이션
EP2AGX190FF35I3G 적합 용도: 6 애플리케이션s: High-Definition Video Broadcast Processing, Wireless Baseband DSP Acceleration, Military Radar Signal Intelligence Preprocessing, ASIC Prototyping and ASIC Replacement, Medical Imaging Pipeline (Ultrasound/CT Front-End), Industrial Machine Vision and Robotics.
High-Definition Video Broadcast Processing
The EP2AGX190FF35I3G's 181,165 logic elements and 10,177,536 bits of embedded block RAM make it well suited to HD/3G-SDI video processing pipelines. With eight onboard multi-gigabit transceivers, the device can ingest multiple SDI/HD-SDI streams simultaneously, perform real-time color-space conversion, frame-rate conversion, and overlay blending, then output processed video through the same transceiver channels. The 612 user I/Os accommodate parallel GPIOs for control-plane interfacing (SPI, I2C, GPIO for downstream video DACs). Industrial temperature grade (-40 °C to +100 °C) supports broadcast equipment deployed in unconditioned outdoor cabinets. Practical benefit: a single FPGA replaces multiple DSP chips and external SRAM, reducing PCB area, BOM cost, and power.
추천
Wireless Baseband DSP Acceleration
Wireless baseband processing for LTE and 5G NR benefits from the EP2AGX190FF35I3G's embedded 18x18 multipliers and high logic density, which deliver parallel MAC operations for FFT, channel estimation, and turbo/LDPC decoding. The 8 multi-gigabit transceivers support CPRI/OBSAI fronthaul links to remote radio heads at 3.072 Gbps to 9.83 Gbps per lane. Industrial temperature grade allows outdoor small-cell deployment. Quantus Prime design tools provide soft-processor (Nios II) and DSP IP cores commonly used for layer-1 acceleration. Trade-off: FPGAs consume more power than ASIC equivalents at scale, but enable field upgrades as 3GPP standards evolve - critical for the 5G NR roadmap.
추천
Military Radar Signal Intelligence Preprocessing
The EP2AGX190FF35I3G supports wideband radar SIGINT preprocessing through its 8 high-speed transceivers feeding into FPGA logic running digital down-conversion (DDC), pulse compression, and CFAR detection. Industrial temp grade plus inherent radiation tolerance of 40 nm bulk CMOS make it deployable in benign-environment military systems (not full MIL-PRF-38535 screened). 612 user I/O support LVDS interfaces to high-speed ADCs like the ADC08D1500, and embedded block RAM holds FFT windows. The Altera/Intel Quartus toolchain provides pre-validated DSP Builder blocks that compress radar algorithm development. Note: full military screening requires a different part; the I3G suffix denotes industrial temp, not MIL-spec.
추천
ASIC Prototyping and ASIC Replacement
The 181,165 logic elements position the EP2AGX190FF35I3G as an ASIC prototyping vehicle for mid-complexity ASICs in the 1-2M gate range. Engineers map RTL (Verilog/VHDL/SystemVerilog) directly via Quartus synthesis and run real-world validation at near-ASIC clock rates. Industrial temperature and high pin count (612 I/O) support verification of complex SoC peripherals. For low-volume production runs where ASIC NRE is uneconomic, the FPGA becomes the production silicon. Pair with off-the-shelf DDR3 controllers and PCIe hard IP. Migration path: as production volumes rise, design teams can re-target to Arria 10 or Cyclone 10 families for newer process nodes.
추천
Medical Imaging Pipeline (Ultrasound/CT Front-End)
The EP2AGX190FF35I3G's 612 user I/Os interface to parallel banks of high-speed ADCs in ultrasound and CT imaging front-ends, while 10,177,536 bits of block RAM hold beamformer delay lines and image reconstruction buffers. Industrial temperature grade supports equipment deployed in controlled clinical environments where ambient temperatures can reach 35-40 °C inside the chassis. The 8 transceivers carry serialized image data to back-end processing FPGAs or processors over low-latency links. Critical for OEMs: predictable supply through last-time-buy status makes it a known-cost component; alternatively, evaluate Cyclone V GX for new designs to avoid future EOL pressure.
추천
Industrial Machine Vision and Robotics
For high-frame-rate machine vision (10 GigE Vision, CoaXPress, Camera Link HS), the EP2AGX190FF35I3G's 8 multi-gigabit transceivers aggregate multiple camera streams for real-time defect detection, robotic guidance, and bin-picking. The 181,165 LE count runs full image-processing chains (canny edge detection, blob analysis, classifier inference) on-chip without external processors. Industrial temperature grade supports factory-floor operation. Practical performance gain: a single Arria II GX FPGA replaces a vision processor plus dedicated ASIC, reducing latency from ms to µs and enabling closed-loop robotic control at kHz rates.
추천
추천 제품 요약
엔지니어링 참조 데이터: EP2AGX190FF35I3G — 비교, 설계 지침 및 규정 준수 정보.
선택 가이드
대체품과의 비교
| 파라미터 | 이 제품 | EP2AGX190FF35I5G | EP2AGX190FF35C6G | EP2AGX125FF35I5G | EP2AGX125FF35I3G |
|---|---|---|---|---|---|
| Package | 1152-ball FC-FBGA (FF35) | 1152-ball FC-FBGA (FF35) - same | 1152-ball FC-FBGA (FF35) - same | 1152-ball FC-FBGA (FF35) - same | 1152-ball FC-FBGA (FF35) - same |
| Brand | Altera (Intel PSG) | Altera (Intel PSG) | Altera (Intel PSG) | Altera (Intel PSG) | Altera (Intel PSG) |
| Logic Elements (LE) | 181,165 | 181,165 (same) | 181,165 (same) | 125,000 (-31%) | 125,000 (-31%) |
| Embedded Memory (bits) | 10,177,536 | 10,177,536 (same) | 10,177,536 (same) | 8,294,400 (-19%) | 8,294,400 (-19%) |
| Temperature Grade | Industrial (-40 °C to +100 °C) | Industrial (same) | Commercial (0 °C to +85 °C) | Industrial (same) | Industrial (same) |
| Speed Grade | 3 (fastest) | 5 (slower) | 6 (slowest) | 5 (slower) | 3 (same) |
| Lifecycle Status | Last-time-buy | Last-time-buy | Last-time-buy | Last-time-buy | Last-time-buy |
주요 차별점
- Highest logic density in the Arria II GX family (vs EP2AGX125FF35I5G)
- Industrial temperature with fastest speed grade (vs EP2AGX190FF35I5G)
- Lead-free RoHS-compliant finish (vs EP2AGX190FF35I3 (without G suffix))
- 8 high-speed transceiver channels (vs Non-transceiver FPGAs of similar LE count)
설계 노트
The 35 mm FC-FBGA flip-chip BGA package concentrates heat at the die. For sustained operation near the 181,165 LE utilization ceiling, attach a copper heat spreader directly to the package lid using thermal interface material (TIM) - the chip is designed for top-side thermal dissipation, not bottom BGA balls. Forced-air cooling alone may be insufficient above 50% utilization; estimate with the Quartus PowerPlay tool before committing to mechanical design. Junction temperature must remain below 100 °C for the I3 (industrial) suffix. Estimated: at 0.9 V core and 80% toggle rate, expect 8-12 W core power dissipation.
The 1152-ball FC-FBGA at 1.0 mm pitch requires a high-density PCB stack-up of at least 12 layers. Use laser-drilled microvias for the inner signal-to-pad escape and standard through-vias for power/ground. Implement a solid ground plane on layer 2 and a power plane on layer 3 to provide low-inductance return paths for the 8 high-speed transceiver channels. Keep the transceiver TX/RX traces length-matched to within 0.13 mm (5 mils) and route over a continuous ground reference plane to control impedance at 100 ohm differential.
The EP2AGX190FF35I3G requires a sequenced power supply: VCC_CORE (0.9 V) ramps first, then VCCIO banks (1.2 V to 3.3 V), then VCCA_PLL and VCCL_GXB. Use a multi-rail controller such as the LTC3566 or ISL8023 with PowerGood output to enforce monotonic startup; Altera/Intel publishes a recommended power-tree reference design in the Arria II GX Device Handbook, Power Management chapter. Decouple each VCC ball with a 0.1 µF X7R plus 10 µF bulk capacitor placed within 2 mm of the ball.
Do not confuse the FF35 (35 mm body) BGA with the EF29 (29 mm body) BGA - despite both being 1152-ball packages, the ball maps differ and they are NOT drop-in on the same PCB. Verifying this is the single most common mistake when migrating between Arria II GX density grades. The 'F' prefix denotes 35 mm body; 'E' denotes 29 mm. Also note that the trailing 'G' suffix is required for lead-free / RoHS-compliant assembly - 'I3' without 'G' indicates a leaded finish that is now restricted under RoHS.
Differential clock inputs (CLK[0]_p/n through CLK[5]_p/n) must be routed as 100 ohm differential pairs with length matching within 0.05 mm. Keep the JTAG chain (TCK, TMS, TDI, TDO) physically short - under 75 mm - and isolated from switching signals to avoid configuration failures. Transceiver TX-to-RX isolation: maintain at least 4x the dielectric thickness between adjacent TX and RX pairs to minimize crosstalk on multi-lane links like PCIe Gen2 or 10 GigE.
규정 준수 정보
Trailing 'G' suffix denotes lead-free / RoHS-compliant finish per Intel/Altera product marking convention. AEC-Q100 is not applicable to FPGAs - this is a logic device, not an automotive analog IC. The 'I' in the MPN suffix denotes industrial temperature grade -40 °C to +100 °C; this is not full MIL-PRF-38535 screening.
