LTC2140CUP-12 - 12-Bit 25Msps Dual-Channel ADC | Analog Devices
부품 번호: LTC2140CUP-12 ✗ 단종| 수량 | 단가 | 합계 |
|---|---|---|
| 1 | $18.5 | $18.50 |
| 10 | $17.2 | $172.00 |
| 100 | $16.25 | $1,625.00 |
| 500 | $15.4 | $7,700.00 |
| 1,000 | $14.8 | $14,800.00 |
LTC2140CUP-12 개요
An ADC (Analog-to-Digital Converter) is a semiconductor device that samples a continuous analog voltage and converts it to a discrete digital code. In the system hierarchy, an ADC sits between an analog front-end (amplifiers, filters, sensors) and a digital signal processor (DSP, FPGA, or microcontroller). Pipelined ADCs such as the LTC2140CUP-12 use a multi-stage architecture that achieves high sample rates with moderate power consumption by interleaving low-resolution stages, trading slightly higher latency for the ability to capture multi-MHz bandwidth signals at low cost.
Key features of the LTC2140CUP-12 include 12-bit resolution, 25 Msps per-channel sample rate, two simultaneously sampled differential or single-ended inputs, a wide input bandwidth, and CMOS or DDR LVDS digital output modes programmable via either a parallel or simple serial interface. The integrated input common-mode buffer and optional digital output randomization further simplify high-performance signal-chain design.
Technically, the part uses a multi-stage pipelined architecture with on-chip sample-and-hold, an internal voltage reference, and a digitally programmable gain. The 64-pin QFN package with exposed pad keeps the loop area compact, which is critical at 25 Msps where clock and input edge rates sit near 100 ps. Programmable output modes and configurable full-scale range allow the ADC to interface directly to FPGAs, ASICs, or standard microcontrollers.
Typical applications for the LTC2140CUP-12 include wireless base-station receiver IF digitizers, handheld signal analyzers, portable imaging systems, ultrasound front ends, and multi-carrier software-defined radio (SDR) platforms. The combination of low power consumption and dual channels makes it particularly attractive for portable and battery-powered test equipment requiring two synchronized acquisition paths.
When designing with this ADC, pay close attention to analog input network layout, decoupling of the internal reference, and the length-matched output routing for DDR LVDS modes. Operating modes are configured through either a parallel CMOS or a simple SPI-style serial interface, allowing all available modes—including output format, gain, and channel selection—to be programmed in-system.
This page synthesizes distributor pricing, drop-in alternatives, parameter-by-parameter comparisons, and practical PCB-level design notes not found in the manufacturer datasheet alone.
드롭인 대체품: LTC2140CUP-12 — 동일 패키지, 핀 호환. PCB 재작업이 필요한 다른 패키지 부품은 제외됩니다.
빠른 비교 도구 — 나란히 비교할 대체 부품을 선택하십시오:
LTC2141CUP-12
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
LTC2142CUP-12
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
LTC2140IUP-12
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
LTC2140CUP-12#PBF
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
LTC2140CUP-12#TRPBF
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
LTC2140CUP-12 최대 정격 & 전기적 특성
| 분해능 | 12 bits |
| Number of Channels | 2 (simultaneous sampling) |
| Sample Rate per Channel | 25 Msps |
| Architecture | Pipelined |
| Input Type | Differential / Single-ended |
| Data Interface | Parallel CMOS / DDR LVDS / Serial SPI (programming) |
| Supply Voltage (Analog) | 1.8 V |
| Supply Voltage (Digital) | 1.8 V / 3.3 V (output driver) |
| 동작 온도 범위 | 0C to +70C (C-suffix) |
| 패키지 | 64-QFN (UP suffix), 9 mm x 9 mm |
| 실장 유형 | Surface Mount |
| Lead-Free / RoHS | Yes (PBF suffix indicates lead-free) |
| Family | LTC2142-12 (65 Msps) / LTC2141-12 (40 Msps) / LTC2140-12 (25 Msps) |
LTC2140CUP-12 64-qfn (up suffix), 9 mm x 9 mm 핀 구성 가이드
LTC2140CUP-12(64-qfn (up suffix), 9 mm x 9 mm 패키지)의 핀 구성입니다. 이 아날로그 부품에는 입력, 출력, 전원 공급 핀이 있습니다. 오프셋 널, 보상, 인에이블 핀 구성은 제조사 데이터시트를 참조하십시오. 신호 컨디셔닝 및 증폭기 회로에 이상적입니다.
다음에 대한 상세 핀아웃 데이터 없음: LTC2140CUP-12.
다음을 참조하십시오: 데이터시트 전체 핀 구성은 다음을 참조하십시오.
일반적인 애플리케이션
LTC2140CUP-12 적합 용도: 6 애플리케이션s: Wireless Base-Station IF Digitizer, Portable Test & Measurement Equipment, Ultrasound Imaging Front End, Software-Defined Radio (SDR) Platforms, Handheld Spectrum Analyzers, Imaging and Industrial Inspection Systems.
Wireless Base-Station IF Digitizer
The LTC2140CUP-12's 12-bit resolution and 25 Msps per-channel rate digitize the intermediate-frequency (IF) outputs of two diversity receiver chains simultaneously, which is essential for base-station digital predistortion loops. Its wide analog input bandwidth preserves multi-carrier envelope information, and DDR LVDS outputs keep the FPGA capture interface compact at this speed. Placed on the IF board between the mixer and the FPGA, the dual simultaneous sampling matches the I/Q timing requirement. Trade-off: 12-bit SNR is sufficient for macro-BTS but not for highest-linearity small-cell applications where 14-bit LTC2174-14 is preferred.
추천
Portable Test & Measurement Equipment
Handheld oscilloscopes, data loggers, and spectrum analyzers benefit from the LTC2140CUP-12's dual 25 Msps channels in a single 9 mm x 9 mm QFN, allowing a 2-channel 12-bit instrument front end from one IC. The 1.8 V analog supply and relatively modest power dissipation suit battery-powered form factors, and the parallel CMOS output mode avoids the complexity of LVDS routing on cost-sensitive portable boards. Compared to a single-channel ADC, the two simultaneously sampled channels enable true differential or trigger-aligned measurements. Trade-off: only 12 bits of vertical resolution, so handheld scopes will not reach the ENOB of 14-bit-class instruments.
추천
Ultrasound Imaging Front End
The two simultaneously sampled 12-bit 25 Msps channels of the LTC2140CUP-12 align well with quadrature (I/Q) or phased-array ultrasound demodulated channels. Its wide analog front-end bandwidth faithfully captures the wideband demodulated signal, and the exposed-pad QFN provides adequate thermal performance for the digitizer stage of a multi-channel board. Designers typically cascade the ADC with an LVDS-capable FPGA or ASIC for back-end beamforming. Trade-off: for higher-channel-count ultrasound systems, designers often step up to a faster ADC family to reduce per-channel board area.
추천
Software-Defined Radio (SDR) Platforms
SDR platforms digitize two baseband I and Q streams, and the LTC2140CUP-12's dual simultaneous sampling preserves the critical phase relationship between I and Q that determines receiver image rejection. Its 25 Msps per-channel rate is sufficient for signals up to roughly 12 MHz baseband bandwidth, ideal for sub-1 GHz amateur and ISM-band SDRs. The serial programming interface allows the host processor to switch between full-scale ranges on the fly to accommodate varying signal levels. Trade-off: 12-bit dynamic range limits sensitivity in weak-signal scenarios, where 14-bit alternatives give meaningful SNR headroom.
추천
Handheld Spectrum Analyzers
Field-deployable spectrum analyzers benefit from the LTC2140CUP-12 because two synchronized 25 Msps 12-bit channels allow direct digitization of an IF chain in a compact form factor, eliminating bulky filters and analog demodulation stages. The 1.8 V analog and digital supplies ease battery-system design, and the parallel CMOS output directly drives a low-cost FPGA without an LVDS bank requirement. Typical designs pair the ADC with a wideband noise-figure-LNA downstream of the RF mixer. Trade-off: limited spurious-free dynamic range at large input levels compared to higher-resolution 14-bit ADCs.
추천
Imaging and Industrial Inspection Systems
Multi-spectral imaging, machine-vision, and industrial inspection systems often use two synchronized analog channels (for example, visible and near-infrared sensors), and the LTC2140CUP-12 provides the dual simultaneous sampling needed for pixel-aligned processing. The 9 mm x 9 mm QFN footprint allows compact camera-head electronics, and its 12-bit resolution is sufficient for typical 8- to 10-bit display pipelines. Designers typically pair it with an FPGA-based image processor for real-time edge detection. Trade-off: for scientific-grade imaging, 14-bit or 16-bit ADCs are preferred to preserve dynamic range in low-contrast scenes.
추천
추천 제품 요약
엔지니어링 참조 데이터: LTC2140CUP-12 — 비교, 설계 지침 및 규정 준수 정보.
선택 가이드
대체품과의 비교
| 파라미터 | 이 제품 | LTC2141CUP-12 | LTC2142CUP-12 | LTC2140IUP-12 |
|---|---|---|---|---|
| Brand | Analog Devices | Analog Devices | Analog Devices | Analog Devices |
| Package | 64-QFN (UP), 9x9 mm | 64-QFN (UP) - same | 64-QFN (UP) - same | 64-QFN (UP) - same |
| Resolution | 12 bits | 12 bits | 12 bits | 12 bits |
| Sample Rate | 25 Msps | 40 Msps | 65 Msps | 25 Msps |
| Number of Channels | 2 (simultaneous) | 2 (simultaneous) | 2 (simultaneous) | 2 (simultaneous) |
| Operating Temperature Range | 0C to +70C | 0C to +70C | 0C to +70C | -40C to +85C |
| Supply Voltage | 1.8 V (analog/digital) | 1.8 V (analog/digital) | 1.8 V (analog/digital) | 1.8 V (analog/digital) |
| Architecture | Pipelined | Pipelined | Pipelined | Pipelined |
| Digital Output | CMOS / DDR LVDS / serial programming | CMOS / DDR LVDS / serial programming | CMOS / DDR LVDS / serial programming | CMOS / DDR LVDS / serial programming |
주요 차별점
- Dual simultaneous sampling at 25 Msps per channel (vs LTC2140 single-channel non-existent (family always dual))
- Pin-compatible upgrade path to higher sample rates (vs LTC2141CUP-12 (40 Msps) and LTC2142CUP-12 (65 Msps))
- Serial (SPI-style) interface supports in-system mode programming (vs Other 12-bit pipelined ADCs in 64-QFN requiring parallel-only configuration)
설계 노트
Estimated: at 25 Msps with 12-bit transitions, edge rates are roughly 1 ns and the analog input loop area must be kept under approximately 5 mm to preserve 12-bit settling. Route AIN+ and AIN- as a tight differential pair over a continuous ground plane, and place the input anti-alias filter within 5 mm of the pins. The QFN exposed pad must be soldered to the inner ground plane through multiple thermal vias (typically 0.3 mm pitch, 9 to 16 vias) to keep junction temperature within limits.
Estimated: a 25 Msps pipelined ADC of this family draws on the order of tens of mW from the 1.8 V analog rail. Use an LC or ferrite-bead pi filter between the system analog 1.8 V LDO and the ADC AVDD pin, and decouple with a 1 uF ceramic in parallel with a 0.01 uF high-frequency capacitor placed within 1 mm of each AVDD pin. Keep the digital DRVDD rail separate from AVDD; if a common 1.8 V supply is used, gate DRVDD with a ferrite to break the return-current coupling.
When using DDR LVDS output mode, route D0-D11 and the DDR clock as 100 ohm differential pairs with intra-pair length matching of approximately 0.5 mm and pair-to-pair matching of approximately 2 mm. Use an FPGA with built-in LVDS-25 input buffers; if the receiver is 3.3 V LVDS, place an AC-coupling capacitor network in series with each pair. For CMOS modes, parallel-terminate the clock to 1.8 V if the FPGA cannot accept the slower CMOS edges directly. Ground-bounce on the digital return is a common cause of spurious tones that masquerade as spurious-free dynamic range problems.
Do not overdrive the analog inputs; signals exceeding the programmed common-mode level cause distortion and clipping that 12-bit performance cannot recover from. Do not run the serial and parallel programming interfaces simultaneously; the SER/PAR pin must be hard-strapped to one mode before reset. Do not skip the REFOUT decoupling; the internal reference requires at least 1 uF to ground for stability. Finally, confirm the family datasheet for the exact SNR/SFDR de-rating with input frequency, since these pipelined ADCs lose roughly 1 dB SNR per 50 MHz of input frequency.
규정 준수 정보
Lead-free (PBF suffix) and RoHS-compliant per Analog Devices product page. Halogen-free and conflict-minerals status not explicitly stated in the datasheet or product page; listed as unknown.
