LTC2156CUP-12 - Dual 12-Bit 210Msps ADC, 64-QFN | Analog Devices
부품 번호: LTC2156CUP-12 ✓ 활성| 수량 | 단가 | 합계 |
|---|---|---|
| 1 | $105 | $105.00 |
| 10 | $99.5 | $995.00 |
| 100 | $95.2 | $9,520.00 |
| 500 | $92.4 | $46,200.00 |
| 1,000 | $90.14 | $90,140.00 |
LTC2156CUP-12 개요
A pipelined ADC is a successive-stage converter architecture that processes one sample per clock cycle after the initial pipeline fill, balancing high sampling rate with moderate die area. Pipelined ADCs sit within the broader hierarchy of analog-to-digital converter -> data converter -> signal chain IC -> mixed-signal semiconductor, and are the dominant topology for converter sampling rates above approximately 50 Msps where successive-approximation (SAR) and flash architectures become impractical.
Key features of the LTC2156CUP-12 include typical DC linearity of ±0.26 LSB INL and ±0.16 LSB DNL, no missing codes over temperature, and a low transition noise of 0.54 LSBRMS. The differential analog inputs accept single-ended or differential drive, and the digital outputs are double-data-rate (DDR) LVDS for low-noise, high-speed interface to an FPGA or ASIC. The ENC+ and ENC- clock inputs can be driven differentially from a sine wave, PECL, LVDS, TTL, or CMOS source, simplifying clock distribution in multi-channel systems.
Typical applications include multi-channel digital oscilloscopes, wideband radar digitizers, software-defined radio receivers, medical imaging front-ends (ultrasound beamformers), and communications test equipment such as vector signal analyzers. The dual-channel integration saves board area versus two discrete single-channel ADCs, and the pin-compatible family allows the same PCB to be populated with the 250 Msps LTC2157-12 or 170 Msps LTC2155-12 depending on system bandwidth needs.
When designing with this part, follow the Analog Devices reference layout for the 64-QFN exposed-pad package: stitch the EP to a solid ground plane with multiple thermal vias, keep analog input traces length-matched and 100 ohm differential, and place the input network and reference decoupling capacitors as close to the pins as possible. The DDR LVDS interface requires careful length matching on the PCB to maintain the 210 Msps data eye margin.
드롭인 대체품: LTC2156CUP-12 — 동일 패키지, 핀 호환. PCB 재작업이 필요한 다른 패키지 부품은 제외됩니다.
이 시리즈의 변형
다음과 드롭인 호환되는 동일 시리즈 모델: LTC2156CUP-12 (동일 폼 팩터 및 풋프린트) — 차이점: Package, Operating Temperature Range, Number of Channels, Resolution, RoHS Status.
빠른 비교 도구 — 나란히 비교할 대체 부품을 선택하십시오:
LTC2157CUP-12
✅ 드롭인✓ 재고 있음
$71.3 / 개
데이터시트 보기 →LTC2155CUP-12
✅ 드롭인✓ 재고 있음
$44.25 / 개
데이터시트 보기 →LTC2145CUP-12
✅ 드롭인✓ 재고 있음
$26.4 / 개
데이터시트 보기 →KAD2710C-17Q68
✅ 드롭인✓ 재고 있음
$24.8 / 개
데이터시트 보기 →LTC2156CUP-12 최대 정격 & 전기적 특성
| 분해능 | 12 bits |
| Number of Channels | 2 (dual) |
| 샘플링 속도 | 210 Msps |
| Architecture | Pipelined |
| Input Type | Differential / Single-ended |
| Digital Output Interface | DDR LVDS |
| INL (typical) | ±0.26 LSB |
| DNL (typical) | ±0.16 LSB |
| Transition Noise | 0.54 LSBRMS |
| Latency | 5 clock cycles |
| Missing Codes | None over temperature |
| Clock Input | Differential (sine, PECL, LVDS, TTL, CMOS) |
| 동작 온도 | -40 C to +85 C (C grade) |
| 패키지 | 64-lead QFN (UP), 9x9 mm with exposed pad |
| 실장 유형 | Surface Mount |
| MSL 레벨 | 3 |
| RoHS 상태 | Compliant (PBF suffix) |
| Family Pin-Compatibility | LTC2157-12 (250 Msps), LTC2155-12 (170 Msps) |
| 1ku List Price (start) | $90.14 (per ADI product page, as of 2026-10-13) |
LTC2156CUP-12 64-lead qfn (up), 9x9 mm with exposed pad 핀 구성 가이드
LTC2156CUP-12(64-lead qfn (up), 9x9 mm with exposed pad 패키지)의 핀 구성입니다. 이 아날로그 부품에는 입력, 출력, 전원 공급 핀이 있습니다. 오프셋 널, 보상, 인에이블 핀 구성은 제조사 데이터시트를 참조하십시오. 신호 컨디셔닝 및 증폭기 회로에 이상적입니다.
다음에 대한 상세 핀아웃 데이터 없음: LTC2156CUP-12.
다음을 참조하십시오: 데이터시트 전체 핀 구성은 다음을 참조하십시오.
일반적인 애플리케이션
LTC2156CUP-12 적합 용도: 6 애플리케이션s: Wideband Digital Oscilloscope Front-End, Software Defined Radio Receiver, Multi-Channel Radar Digitizer, Ultrasound Beamforming Front-End, Vector Signal Analyzer Capture, Communications Test Equipment.
Wideband Digital Oscilloscope Front-End
The LTC2156CUP-12's 210 Msps sample rate and dual-channel integration make it well suited for a 2-channel 100 MHz bandwidth digital oscilloscope input stage. The 12-bit resolution captures small signal details while the DDR LVDS output streams data directly into an FPGA for triggering and display. Designers place the converter between the front-end attenuator/buffer and the FPGA, with length-matched 100 ohm differential input traces to preserve the 70 dBFS SNR at the analog input. The exposed-pad 64-QFN package allows a compact 4-layer PCB layout with solid ground and thermal vias.
추천
Software Defined Radio Receiver
In a software-defined radio, the LTC2156CUP-12 simultaneously digitizes the I and Q baseband outputs of a quadrature demodulator at 210 Msps, capturing up to 105 MHz of instantaneous bandwidth per channel. The 5 clock cycle pipeline latency enables closed-loop AGC and digital predistortion algorithms, and the DDR LVDS interface feeds a DSP or FPGA running the demodulation stack. The pipelined architecture's no-missing-codes guarantee and 0.54 LSBRMS transition noise preserve signal fidelity for weak-signal reception. Typical SDR boards pair the ADC with an RF front-end LNA, mixer, and a low-jitter clock generator.
추천
Multi-Channel Radar Digitizer
Phased-array and MIMO radar systems use multiple synchronized ADC channels to capture returning echoes across the antenna array. The LTC2156CUP-12's dual 12-bit 210 Msps channels allow a single chip to digitize two radar receive paths with channel-to-channel skew controlled by the same ENC+ / ENC- differential clock. The pipelined architecture's 5-cycle latency is deterministic and matches across channels, which simplifies beamforming calibration. The 64-QFN exposed-pad package provides adequate thermal margin for the 1.7 V analog and 1.8 V digital supplies typical in radar hardware.
추천
Ultrasound Beamforming Front-End
Medical ultrasound imaging systems require 32 to 256 synchronized receive channels to beamform returning echoes from the patient. Each LTC2156CUP-12 captures two adjacent transducer channels at 210 Msps, halving the ADC count and PCB area compared to single-channel converters. The 12-bit dynamic range is sufficient for low-MHz harmonic imaging, and the DDR LVDS output allows dense channel routing over a small backplane. Beamforming firmware runs on a downstream FPGA, with the deterministic 5-cycle pipeline latency preserving inter-channel phase coherence required for accurate beam steering.
추천
Vector Signal Analyzer Capture
A vector signal analyzer digitizes modulated RF signals for demodulation, modulation-error-rate analysis, and EVM measurement. The LTC2156CUP-12's 12-bit resolution and 210 Msps enable capture of 80 MHz-wide modulated signals such as LTE and 5G NR carriers with sub-1% EVM. The dual channel allows simultaneous capture of a signal and a reference path, or a main and adjacent channel for ACLR measurement. The DDR LVDS output streams data into an FPGA or DSP for real-time FFT and demodulation, and the 64-QFN package is small enough to fit in a portable bench instrument form factor.
추천
Communications Test Equipment
The LTC2156CUP-12 is widely used in production test equipment for cellular base stations, WLAN, and IoT radios. The dual 12-bit 210 Msps channels allow simultaneous digitisation of a transmitter output and a reference signal for cross-correlation and gain/phase imbalance measurement. The pipelined architecture with 5-cycle latency and no missing codes supports high-throughput automated test where hundreds of devices per hour must be characterised. The 64-QFN exposed-pad package supports reflow soldering with standard SAC305 lead-free profiles, simplifying manufacturing.
추천
추천 제품 요약
엔지니어링 참조 데이터: LTC2156CUP-12 — 비교, 설계 지침 및 규정 준수 정보.
선택 가이드
대체품과의 비교
| 파라미터 | 이 제품 | LTC2157CUP-12 | LTC2155CUP-12 | LTC2145CUP-12 |
|---|---|---|---|---|
| Package | 64-QFN (UP, 9x9 mm) with exposed pad | 64-QFN (UP, 9x9 mm) - same | 64-QFN (UP, 9x9 mm) - same | 64-QFN (UP, 9x9 mm) - same |
| Brand | Analog Devices (formerly Linear Technology) | Analog Devices - same | Analog Devices - same | Analog Devices - same |
| Resolution | 12 bits | 12 bits | 12 bits | 14 bits |
| Sampling Rate | 210 Msps | 250 Msps | 170 Msps | 125 Msps |
| Number of Channels | 2 (dual) | 2 (dual) | 2 (dual) | 2 (dual) |
| Digital Output Interface | DDR LVDS | DDR LVDS | DDR LVDS | DDR LVDS |
| INL (typical) | ±0.26 LSB | ±0.26 LSB | ±0.26 LSB | ±1.5 LSB (14-bit) |
| Pin Compatibility | Reference | Drop-in (same family) | Drop-in (same family) | Drop-in (different resolution, same footprint) |
주요 차별점
- Drop-in pin-compatible with 250 Msps and 170 Msps family members (vs LTC2157CUP-12 (250 Msps) and LTC2155CUP-12 (170 Msps))
- Dual 12-bit channels in a single package (vs Discrete single-channel 12-bit 210 Msps ADCs)
- DDR LVDS output reduces pin count and EMI vs parallel CMOS (vs Parallel CMOS-output ADCs at the same sample rate)
설계 노트
Use the Analog Devices reference PCB land pattern for the 64-QFN (UP) package. Stitch the exposed pad (EP) to a solid analog ground plane with a 3x3 grid of 0.3 mm thermal vias for low thermal resistance. Place input network, common-mode reference, and bypass capacitors within 2 mm of the respective pins. Route AIN+/AIN- and BIN+/BIN- differential pairs as 100 ohm matched-length traces on the top layer over a continuous ground pour.
The ENC+ and ENC- differential clock must be driven from a low-jitter source (typically < 200 fs RMS jitter) to achieve the datasheet SNR. Using a noisy CMOS clock will degrade aperture jitter and reduce the effective number of bits at high input frequencies. The Analog Devices AD9516 clock generator family is recommended for multi-channel systems requiring inter-channel skew control.
The DDR LVDS data and clock outputs must be length-matched to within 25 mil (0.6 mm) of the target FPGA LVDS pins to maintain the data eye margin at 210 Msps. Use 100 ohm differential routing with 50 ohm single-ended impedance, and add a 100 ohm termination resistor at the FPGA end. Series-stuff 100 ohm resistors close to the ADC output pins can also be used for source-series termination if FPGA receivers are placed within 50 mm.
Decouple each analog and digital supply pin with a 0.1 uF ceramic capacitor placed within 2 mm of the pin, plus a 10 uF tantalum or polymer bulk capacitor near the package. Use a ferrite bead to isolate the ADC analog supply from upstream switching converter noise. Sharing the analog and digital grounds via a single connection point under the exposed pad prevents ground-loop currents from coupling into sensitive analog inputs.
Estimated: at typical operating power of approximately 1 W per channel, the 64-QFN (UP) package requires an adequate copper pour (at least 1 sq inch on top and bottom layers) to keep junction temperature below +125 C. In enclosed housings or stacked-board designs, add forced-air cooling. The exposed pad is the primary thermal path - failure to solder it will increase junction temperature by 30-40 C and risk thermal shutdown.
규정 준수 정보
Lead-free, RoHS and REACH compliant per the #PBF suffix and Analog Devices product page. Not AEC-Q100 qualified (industrial C grade, 0 to +70 C or -40 to +85 C operating temperature). Halogen-free status not specified in available data.
