LTC2172CUKG-12 - 12-Bit 65Msps Quad ADC LVDS | Analog Devices
부품 번호: LTC2172CUKG-12 ✓ 활성| 수량 | 단가 | 합계 |
|---|---|---|
| 1 | $51.63 | $51.63 |
| 10 | $48.5 | $485.00 |
| 100 | $42 | $4,200.00 |
| 500 | $37.5 | $18,750.00 |
| 1,000 | $33 | $33,000.00 |
LTC2172CUKG-12 개요
An ADC (analog-to-digital converter) is a semiconductor that converts continuous analog waveforms into discrete digital codes at a specified sample rate. Quad ADCs such as the LTC2172CUKG-12 integrate four independent conversion channels on a single die, allowing simultaneous sampling of multiple signals - useful in MIMO transceivers, multi-antenna base stations, medical imaging arrays, and beamforming systems. Low-power quad ADCs sit at the intersection of high-speed data conversion and energy-efficient system design, supporting both battery-powered portable instruments and dense multi-channel rack equipment.
Key specifications for the LTC2172CUKG-12 include 65 Msps sampling rate, 12-bit resolution, LVDS digital outputs with 3.5 mA drive and 1.25 V common-mode voltage, 1.8 V single-supply operation, 800 MHz full-power analog input bandwidth, integrated sample-and-hold, configurable shutdown and nap modes, and an SPI configuration port for register control. The selectable input range (1 V P-P or 2 V P-P) enables direct interfacing to a wide range of IF/RF signal chains without external attenuators.
Architecturally, the LTC2172CUKG-12 uses a pipelined multi-stage ADC core per channel, which provides an excellent speed-resolution trade-off: each stage resolves a few bits and passes the residue to the next, allowing very high clock rates while keeping per-stage capacitor area modest. Differential analog inputs with on-chip common-mode bias simplify transformer or op-amp driver interfacing.
Typical applications include 4G LTE and diversity radio receiver basebands, multi-channel communications test equipment, handheld and portable imaging systems, medical ultrasound front-ends, and multi-antenna phased-array radar digitizers. Its low power draw makes it suitable for thermally constrained enclosures.
When designing with this device, AC-couple or DC-couple the analog inputs through a differential driver, place the LVDS 100 Ω termination resistors as close as possible to the FPGA/ASIC LVDS pins, and use a low-noise LDO (such as the ADP1740) to derive the 1.8 V analog supply from a switching pre-regulator.
This page synthesizes distributor pricing, drop-in pin-compatible alternatives, and practical design guidance not found in the manufacturer datasheet alone.
드롭인 대체품: LTC2172CUKG-12 — 동일 패키지, 핀 호환. PCB 재작업이 필요한 다른 패키지 부품은 제외됩니다.
이 시리즈의 변형
다음과 드롭인 호환되는 동일 시리즈 모델: LTC2172CUKG-12 (동일 폼 팩터 및 풋프린트) — 차이점: Package, Resolution, Digital Output Interface, Pin Compatibility, Sampling Rate.
빠른 비교 도구 — 나란히 비교할 대체 부품을 선택하십시오:
LTC2172CUKG-14
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
LTC2171CUKG-12
✅ 드롭인✓ 재고 있음
$24 / 개
데이터시트 보기 →LTC2171CUKG-14
✅ 드롭인✓ 재고 있음
$26.75 / 개
데이터시트 보기 →LTC2170CUKG-12
✅ 드롭인✓ 재고 있음
$20.65 / 개
데이터시트 보기 →LTC2171IUKG-12
✅ 드롭인✓ 재고 있음
$23.3 / 개
데이터시트 보기 →LTC2172CUKG-12 최대 정격 & 전기적 특성
| 분해능 | 12 bits |
| Number of Channels | 4 (simultaneous sampling) |
| Sample Rate | 65 Msps |
| Architecture | Pipelined |
| 공급 전압 | 1.8 V (single) |
| Input Range | 1 V P-P to 2 V P-P selectable |
| Analog Input Type | Differential |
| Input Bandwidth | 800 MHz full power |
| Digital Output | LVDS (3.5 mA, 1.25 V common mode) |
| Output Termination | 100 Ω differential per LVDS pair |
| Power Modes | Shutdown and Nap modes |
| Configuration Interface | Serial SPI port |
| 패키지 | 52-pin QFN (7 mm × 8 mm) |
| 실장 유형 | Surface Mount |
| RoHS 상태 | Compliant (PBF suffix) |
| Pin Compatibility | Pin-compatible with LTC2172-14, LTC2171-12, LTC2170-12 |
LTC2172CUKG-12 52-pin qfn (7 mm × 8 mm) 핀 구성 가이드
LTC2172CUKG-12(52-pin qfn (7 mm × 8 mm) 패키지)의 핀 구성입니다. 이 아날로그 부품에는 입력, 출력, 전원 공급 핀이 있습니다. 오프셋 널, 보상, 인에이블 핀 구성은 제조사 데이터시트를 참조하십시오. 신호 컨디셔닝 및 증폭기 회로에 이상적입니다.
다음에 대한 상세 핀아웃 데이터 없음: LTC2172CUKG-12.
다음을 참조하십시오: 데이터시트 전체 핀 구성은 다음을 참조하십시오.
일반적인 애플리케이션
LTC2172CUKG-12 적합 용도: 6 애플리케이션s: 4G LTE Diversity Radio Receiver Baseband, Multi-Channel Communications Test Equipment, Portable Multi-Channel Imaging System, Medical Ultrasound Front-End Digitizer, Multi-Antenna Phased-Array Radar Digitizer, MIMO Wireless Testbed Digitizer.
4G LTE Diversity Radio Receiver Baseband
The LTC2172CUKG-12 fits 4G LTE diversity receivers because its four simultaneously-sampling 65 Msps channels digitize dual-antenna I/Q baseband signals while maintaining phase alignment between paths. Each channel's 800 MHz input bandwidth accommodates wideband LTE carriers, and the LVDS outputs feed directly into FPGAs without level translation. A 1.8 V single supply simplifies power tree design compared to parts requiring separate analog and digital rails. Selectable 1 V P-P / 2 V P-P input ranges let designers match the ADC full-scale to the upstream transceiver output without external attenuators.
추천
Multi-Channel Communications Test Equipment
Test and measurement instruments benefit from the LTC2172CUKG-12's four 12-bit 65 Msps channels because one IC replaces four discrete ADCs, reducing board area while preserving per-channel sample-rate throughput. The integrated sample-and-hold eliminates inter-channel skew that would otherwise compromise phase-coherent multi-tone measurements such as EVM and ACLR tests on wireless transmitters. SPI configuration lets the test set programmer reconfigure input range and power modes dynamically per test step. The 1.8 V single supply and low power draw reduce cooling requirements in dense rack-mount test platforms.
추천
Portable Multi-Channel Imaging System
Portable imaging systems such as industrial borescopes and handheld flaw detectors use the LTC2172CUKG-12 to digitize four CMOS/CCD sensor outputs simultaneously. Its low power profile extends battery runtime versus alternative higher-speed ADCs, while the 12-bit resolution captures dynamic range typical of X-ray and fluorescence imaging. Shutdown and nap modes turn off idle channels to save power when only a subset of sensors is active. The compact 7 mm × 8 mm QFN fits tight camera-head enclosures.
추천
Medical Ultrasound Front-End Digitizer
The LTC2172CUKG-12 suits medical ultrasound receivers because four channels captured simultaneously preserve the relative phase and amplitude needed for beamforming. Each channel's 800 MHz analog bandwidth handles the wide dynamic range of returned echoes from deep tissue penetration. The 12-bit resolution is sufficient for B-mode grayscale imaging, and the LVDS outputs deliver samples to the back-end FPGA across shielded cables with strong common-mode rejection. Shutdown modes let handheld units disable unused channels to extend battery life between scans.
추천
Multi-Antenna Phased-Array Radar Digitizer
Phased-array radar systems use the LTC2172CUKG-12 to digitize multiple antenna channels simultaneously for digital beamforming. Simultaneous sampling preserves the relative phase across the array, which directly determines beam-steering accuracy. The four-channel density cuts board area versus using single-channel ADCs, allowing more antenna elements in a constrained footprint. The 1.8 V single supply simplifies power distribution through the antenna manifold. Designers typically pair this ADC with an FPGA that performs fast Fourier transforms on the LVDS streams in real time.
추천
MIMO Wireless Testbed Digitizer
MIMO wireless testbeds need synchronized multi-channel capture, and the LTC2172CUKG-12 provides four simultaneous 65 Msps channels in a single QFN package. The SPI configuration port allows testbed firmware to dynamically switch input range and power modes for different modulation standards such as Wi-Fi 6E and 5G NR. The differential analog inputs accept direct transformer coupling from RF downconverter outputs. Low power consumption enables portable field-test configurations.
추천
추천 제품 요약
엔지니어링 참조 데이터: LTC2172CUKG-12 — 비교, 설계 지침 및 규정 준수 정보.
선택 가이드
대체품과의 비교
| 파라미터 | 이 제품 | LTC2172CUKG-14 | LTC2171CUKG-12 | LTC2171CUKG-14 | LTC2170CUKG-12 | LTC2171IUKG-12 |
|---|---|---|---|---|---|---|
| Brand | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices |
| Package | 52-pin QFN (7x8 mm) | 52-pin QFN (7x8 mm) - same | 52-pin QFN (7x8 mm) - same | 52-pin QFN (7x8 mm) - same | 52-pin QFN (7x8 mm) - same | 52-pin QFN (7x8 mm) - same |
| Resolution | 12 bits | 14 bits | 12 bits | 14 bits | 12 bits | 12 bits |
| Sample Rate | 65 Msps | 65 Msps | 40 Msps | 40 Msps | 25 Msps | 40 Msps |
| Number of Channels | 4 | 4 | 4 | 4 | 4 | 4 |
| Supply Voltage | 1.8 V | 1.8 V | 1.8 V | 1.8 V | 1.8 V | 1.8 V |
| Digital Output | LVDS | LVDS | LVDS | LVDS | LVDS | LVDS |
| Temperature Grade | Commercial | Commercial | Commercial | Commercial | Commercial | Industrial |
주요 차별점
- Pin-compatible 12-bit and 14-bit upgrade path in the same QFN package (vs LTC2172CUKG-14)
- Same QFN footprint at 40 Msps for cost-down SKUs (vs LTC2171CUKG-12)
- Industrial temperature grade available in same package (vs LTC2171IUKG-12)
- Lower power alternative at 25 Msps (vs LTC2170CUKG-12)
설계 노트
The LTC2172CUKG-12 is designed to operate from a single 1.8 V supply. Place a low-noise LDO such as the Analog Devices ADP1740 immediately after any switching pre-regulator to keep switching ripple out of the analog and clock domains. Estimated: at 65 Msps with all four channels active, the part draws roughly the maximum power specified in the datasheet; derate the LDO with at least 20% margin. Decouple the 1.8 V pin with a 1 µF ceramic plus a 0.1 µF high-frequency bypass placed within 2 mm of the pin.
Each LVDS output pair requires a 100 Ω differential termination resistor at the receiver end. Route LVDS traces as tightly coupled differential pairs with 100 Ω differential impedance; keep trace length matching to within 150 mil (3.8 mm) across pairs to avoid inter-channel skew. Per the LTC2172-12 datasheet, the analog inputs should be driven differentially through a balun or a fully differential driver (such as the AD8138) for best harmonic performance at 65 Msps.
Source the LTC2172CUKG-12 sample clock from a low-jitter clock generator such as the AD9516, and keep the clock trace short and impedance-controlled. The integrated sample-and-hold requires stable clock edges with jitter well below 1 ps RMS to preserve SNR at 65 Msps. Place the clock driver close to the ADC clock input pin and provide a dedicated ground via. Estimated: every additional 1 ps of clock jitter reduces SNR by approximately 0.5 dB at the Nyquist input frequency.
Estimated: at full 65 Msps with four channels active, the LTC2172CUKG-12 dissipates approximately the maximum power quoted in the datasheet. The 52-pin QFN has an exposed pad that must be soldered to a continuous ground plane with multiple thermal vias to keep junction temperature in spec. Limit ambient operating temperature to 70 °C or less in sealed enclosures, or specify the industrial-temperature LTC2171IUKG-12 variant for harsh environments.
Common pitfalls include: (1) omitting the 100 Ω LVDS termination, which causes reflections and corrupted samples; (2) using a single-ended analog input instead of differential, which halves SNR; (3) routing LVDS pairs with mismatched lengths, which creates inter-channel timing skew; (4) failing to solder the QFN exposed pad, which prevents thermal relief and may cause device failure in production; (5) leaving unused channels powered instead of using shutdown/nap modes, which wastes power.
규정 준수 정보
RoHS compliance indicated by the #PBF suffix per the DigiKey listing; AEC-Q100 automotive qualification not applicable for this commercial-grade ADC
