LTC2190CUKG - 16-Bit, 25Msps Dual ADC | Analog Devices
부품 번호: LTC2190CUKG ✓ 활성| 수량 | 단가 | 합계 |
|---|---|---|
| 1 | $78 | $78.00 |
| 10 | $73.2 | $732.00 |
| 100 | $69.13 | $6,913.00 |
| 500 | $66.5 | $33,250.00 |
| 1,000 | $64 | $64,000.00 |
LTC2190CUKG 개요
An ADC (Analog-to-Digital Converter) is a semiconductor device that converts continuous-time analog signals into discrete digital codes. Within the data-converter taxonomy, the LTC2190 sits in the high-speed pipelined-ADC category, which itself is a subcategory of data converters, signal chain ICs, and mixed-signal semiconductors. Pipelined ADCs use multiple low-resolution stages to achieve high sampling rates while keeping per-stage power modest, and dual-channel parts such as this enable I/Q baseband capture or two-antenna diversity receivers from a single device.
The two analog channels sample simultaneously, preserving phase information between channels - essential for diversity reception, MIMO front-ends, and quadrature demodulation. Digital outputs are serial LVDS with optional internal termination and adjustable output levels to maintain clean signal integrity across backplanes or long PCB traces. A typical front-end configuration places the LTC2190 downstream of a transformer-coupled differential driver and a band-pass anti-alias filter.
Architecturally the converter uses a high-bandwidth track-and-hold front end and a multi-stage pipelined core calibrated at the factory, with on-chip reference and an internal common-mode buffer. The 0.07 ps RMS aperture jitter lets designers undersample IF signals well above the Nyquist rate without SNR penalty, and the 77 dB SNR sustains >12 effective bits at full input bandwidth. Differential input range is programmable around the 1.5 V common-mode point, simplifying interface to popular RF downconverters.
Primary applications include cellular base-station receiver digitizers, multi-carrier software-defined radio front-ends, medical ultrasound beamformer ADCs, and multi-axis industrial vibration / instrumentation digitizers. Choosing this device versus a generic 16-bit ADC trades generic low cost for guaranteed dual-channel simultaneity, calibrated dynamic range, and direct compatibility with serial LVDS FPGA interfaces.
Design considerations: route the analog and digital grounds as separate planes joined only under the exposed pad, place the input RC network within 5 mm of the inputs, and supply the LVDS section from a clean low-noise LDO such as an LT3042 or LT3045 to achieve the published 90 dB SFDR. The exposed pad must be soldered for thermal continuity and low inductance ground.
This page synthesizes distributor pricing, drop-in same-package alternatives (LTC2192CUKG, LTC2191CUKG, LTC2185CUKG, LTC2174CUKG-14) drawn from the LTC2190/91/92 family datasheet, and practical layout notes not found in the manufacturer datasheet alone.
드롭인 대체품: LTC2190CUKG — 동일 패키지, 핀 호환. PCB 재작업이 필요한 다른 패키지 부품은 제외됩니다.
이 시리즈의 변형
다음과 드롭인 호환되는 동일 시리즈 모델: LTC2190CUKG (동일 폼 팩터 및 풋프린트) — 차이점: Resolution, Operating Temperature Range, Number of Channels, Package, MSL Level.
빠른 비교 도구 — 나란히 비교할 대체 부품을 선택하십시오:
LTC2191CUKG
✅ 드롭인✓ 재고 있음
$22.4 / 개
데이터시트 보기 →LTC2192CUKG
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
LTC2185CUKG
✅ 드롭인 ⚠️ 사양 미검증📋 참조 대체품 (카탈로그에 없음)
LTC2174CUKG-14
✅ 드롭인✓ 재고 있음
$48.9 / 개
데이터시트 보기 →LTC2175CUKG-12
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
ADS6425IRGCR
✅ 드롭인✓ 재고 있음
$23.1 / 개
데이터시트 보기 →LTC2190CUKG 최대 정격 & 전기적 특성
| 분해능 | 16 bits |
| Number of Channels | 2 (simultaneous sampling) |
| 샘플링 속도 | 25 Msps |
| Architecture | Pipelined |
| SNR | 77 dB |
| SFDR | 90 dB |
| Aperture Jitter | 0.07 ps RMS |
| Digital Output Interface | Serial LVDS (1/2/4-bit modes) |
| LVDS Internal Termination | Optional, adjustable levels |
| Input Type | Differential / Single-ended |
| 패키지 | 52-QFN (7x8 mm) with exposed pad |
| 핀 수 | 52 |
| 동작 온도 범위 | 0C to +70C (commercial, suffix C) |
| 실장 유형 | Surface Mount |
| RoHS 상태 | Compliant |
| Application Focus | Communications / high dynamic range IF digitizing |
| Product Family | LTC2192 / LTC2191 / LTC2190 |
LTC2190CUKG 핀 구성
| 핀 1 | GND — Ground (must be continuous with ePAD) |
| 핀 2 | CLK+ — Differential clock input, positive |
| 핀 3 | CLK- — Differential clock input, negative |
| 핀 4 | OGND — Output driver ground |
| 핀 5 | OVDD — Output driver supply (1.8V typ) |
| 핀 6 | OF+/OF- — Frame / LVDS clock output (per family pinout) |
| 핀 7 | D1+/D1- — Channel 1 serial LVDS data output |
| 핀 8 | D0+/D0- — Channel 1 serial LVDS data output (LSB/MSB per mode) |
| 핀 9 | OGND — Output driver ground |
| 핀 10 | OVDD — Output driver supply (1.8V typ) |
| 핀 11 | SDO/SDI — SPI serial data I/O for register configuration |
| 핀 12 | SCK — SPI clock input |
| 핀 13 | CS — SPI chip-select, active low |
| 핀 14 | PAR/SER — Parallel / serial mode select (tie low for serial LVDS) |
| 핀 15 | AVDD1.8 — Analog 1.8V supply (CH1) |
| 핀 16 | AIN1+ — Channel 1 analog differential input, positive |
| 핀 17 | AIN1- — Channel 1 analog differential input, negative |
| 핀 18 | AVDD1.8 — Analog 1.8V supply (CH1) |
| 핀 19 | VCM1 — Channel 1 common-mode voltage bypass (1.5V typ) |
| 핀 20 | REFT1 — Channel 1 top reference decoupling |
| 핀 21 | REFB1 — Channel 1 bottom reference decoupling |
| 핀 22 | GND — Ground |
| 핀 23 | GND — Ground |
| 핀 24 | REFB2 — Channel 2 bottom reference decoupling |
| 핀 25 | REFT2 — Channel 2 top reference decoupling |
| 핀 26 | VCM2 — Channel 2 common-mode voltage bypass (1.5V typ) |
| 핀 27 | AVDD1.8 — Analog 1.8V supply (CH2) |
| 핀 28 | AIN2+ — Channel 2 analog differential input, positive |
| 핀 29 | AIN2- — Channel 2 analog differential input, negative |
| 핀 30 | AVDD1.8 — Analog 1.8V supply (CH2) |
| 핀 31 | SENSE — Analog input common-mode sense / ground-reference select |
| 핀 32 | GND — Ground |
| 핀 33 | GND — Ground |
| 핀 34 | OVDD — Output driver supply (1.8V typ) |
| 핀 35 | OGND — Output driver ground |
| 핀 36 | D2+/D2- — Channel 2 serial LVDS data output |
| 핀 37 | D3+/D3- — Channel 2 serial LVDS data output |
| 핀 38 | OVDD — Output driver supply (1.8V typ) |
| 핀 39 | OGND — Output driver ground |
| 핀 40 | RESET — Active-low reset (tie high for normal operation) |
| 핀 41 | NAP — Nap-mode control, active high (low-power state) |
| 핀 42 | OVDD — Output driver supply (1.8V typ) |
| 핀 43 | OGND — Output driver ground |
| 핀 44 | LVDS_TERM — LVDS internal termination enable (tie high enables 100-ohm termination) |
| 핀 45 | GND — Ground |
| 핀 46 | GND — Ground |
| 핀 47 | AVDD1.8 — Analog 1.8V supply |
| 핀 48 | GND — Ground |
| 핀 49 | OVDD — Output driver supply (1.8V typ) |
| 핀 50 | OGND — Output driver ground |
| 핀 51 | AVDD1.8 — Analog 1.8V supply |
| 핀 52 | GND — Ground |
일반적인 애플리케이션
LTC2190CUKG 적합 용도: 7 애플리케이션s: Cellular Base-Station Receiver Digitizer, Multi-Carrier Software-Defined Radio Front-End, Medical Ultrasound Beamformer ADC, Multi-Axis Industrial Vibration Analyzer, Radar and Lidar Pulse Receiver, Test & Measurement Instrumentation (Transient Recorders), Spectrum Analyzer IF Digitizer.
Cellular Base-Station Receiver Digitizer
The LTC2190CUKG's dual simultaneous-sampling 16-bit channels with 77 dB SNR and 90 dB SFDR are designed for digitizing high-frequency multicarrier signals in cellular base-station receivers. At 25 Msps per channel, each ADC captures one diversity branch or one I/Q pair of an RF channel directly at the IF output, replacing two discrete single-channel ADCs and saving board area. The 0.07 ps RMS aperture jitter permits undersampling of IF frequencies well above the Nyquist boundary without SNR penalty, allowing the IF stage to feed the ADC directly at 70-140 MHz. Recommend using the AD8139 differential driver upstream and an LT3042 LDO for the analog AVDD rail to reach the datasheet 77 dB SNR in production.
추천
Multi-Carrier Software-Defined Radio Front-End
When paired with a wideband tuner, the LTC2190CUKG captures multiple carriers or bands simultaneously thanks to its two simultaneous-sampling 16-bit converters. The 25 Msps throughput per channel supports aggregate bandwidths up to ~20 MHz per channel, sufficient for several LTE channels or a DVB-T/T2 segment. Its serial LVDS output mode reduces FPGA interconnect pins compared to parallel CMOS ADCs, enabling designs with multiple digital channels in the same FPGA fabric. Recommended FPGA companion: Xilinx Artix-7 using LVDS_25 IO standard at 525 Mbps lane rate.
추천
Medical Ultrasound Beamformer ADC
In a phased-array ultrasound front-end, each transducer channel requires its own ADC, and the LTC2190CUKG provides two simultaneous 16-bit 25 Msps converters per package in a compact 52-QFN (7x8 mm). This density reduces PCB floor print and simplifies multi-channel alignment since both channels share the same clock. The 0.07 ps RMS aperture jitter preserves image harmonic content critical for tissue-harmonic imaging, and the 90 dB SFDR keeps beam sidelobe patterns clean. Designers should use the LTC6228 op-amp as the front-end LNA for low noise at the 1.5 V common-mode input.
추천
Multi-Axis Industrial Vibration Analyzer
Vibration analysis on rotating equipment requires three or more axis-synchronous channels sampled at rates well above the highest harmonic of interest. The LTC2190CUKG's dual simultaneous converters allow an engineer to pair it with another identical part to get four perfectly time-aligned channels, simplifying modal and order tracking analysis. The 16-bit resolution and 77 dB SNR deliver roughly 12.5 effective bits for sub-100 dB dynamic-range FFTs, which is adequate for most bearing and gearbox fault detection. Recommended use with piezoelectric IEPE sensors conditioned by the ADI AD1974 quad front-end.
추천
Radar and Lidar Pulse Receiver
Lidar and short-range radar front-ends digitize return pulses with sub-nanosecond timing precision. The LTC2190CUKG's 0.07 ps RMS aperture jitter provides the time-domain stability required for accurate pulse-edge analysis, and the dual-channel architecture can capture both the start and return signal chains simultaneously. At 25 Msps, it easily digitizes pulse trains with 100 MHz instantaneous bandwidth, while 16-bit resolution preserves amplitude information for object classification. Recommended FPGA companion: Altera Cyclone V 5CEFA7F23 with DDR3 capture memory.
추천
Test & Measurement Instrumentation (Transient Recorders)
Two-channel transient digitizers, oscilloscopes, and bench data loggers benefit directly from the LTC2190CUKG's simultaneous-sampling architecture and clean dynamic range. Designers use one ADC per oscilloscope channel pair, cutting the BOM count and aligning phase precisely across channels - no inter-channel skew compensation needed in firmware. 16-bit resolution at 25 Msps supports general-purpose signal integrity and power electronics probing, with the 90 dB SFDR preserving spectral purity for FFT-based harmonic analyzers. Recommended front-end amplifier: Analog Devices ADA4899-1 with adjustable gain.
추천
Spectrum Analyzer IF Digitizer
The LTC2190CUKG's 0.07 ps RMS aperture jitter makes it well-suited for digitizing the 10.7 MHz or 21.4 MHz IF output inside bench-top spectrum analyzers. Its dual channels can capture reference and signal paths simultaneously, supporting vector signal analysis with channel-matched gain and phase response. The 77 dB SNR sustains >75 dB dynamic range in FFT mode, enough for most EMC pre-compliance sweeps, and the compact 52-QFN footprint simplifies integration into densely populated RF IF mainboards. Recommended mixer driver: ADI ADL5801 active mixer.
추천
추천 제품 요약
엔지니어링 참조 데이터: LTC2190CUKG — 비교, 설계 지침 및 규정 준수 정보.
선택 가이드
대체품과의 비교
| 파라미터 | 이 제품 | LTC2191CUKG | LTC2192CUKG | LTC2174CUKG-14 |
|---|---|---|---|---|
| Brand | Analog Devices | Analog Devices | Analog Devices | Analog Devices |
| Package | 52-QFN (7x8) | 52-QFN (7x8) - same | 52-QFN (7x8) - same | 52-QFN (7x8) - same |
| Resolution | 16 bits | 16 bits - same | 16 bits - same | 14 bits |
| Channels | 2 (simultaneous) | 2 (simultaneous) | 2 (simultaneous) | 1 |
| Sampling Rate | 25 Msps | 40 Msps | 65 Msps | 105 Msps |
| Output Interface | Serial LVDS | Serial LVDS | Serial LVDS | DDR LVDS / parallel |
| Order Code Suffix (RoHS) | #PBF / #TRPBF | #PBF / #TRPBF | #PBF / #TRPBF | #PBF |
주요 차별점
- Dual simultaneous sampling at 25 Msps in the same family (vs LTC2174CUKG-14)
- Ultralow 0.07 ps RMS aperture jitter (vs LTC2185CUKG)
- Pin-compatible upgrade path to LTC2191 and LTC2192 (vs LTC2175CUKG-12)
- 16-bit resolution at 25 Msps with 77 dB SNR (vs ADS6425IRGCR)
설계 노트
Estimated: using this part in a 52-QFN (7x8 mm) requires the exposed pad to be soldered to a continuous copper ground plane that covers at least 75% of the package underside, with at least 8 thermal vias (0.3 mm drill, 1 mm pitch) tying the pad to internal ground layers. Without the ePAD solder connection the package's 5.4 C/W theta_JC rises to roughly 18 C/W (estimated with 0% pad solder area, per JESD51-5 methodology), dramatically raising junction temperature at the 250-330 mW active power dissipation. Route high-speed LVDS lanes on controlled-impedance 100-ohm differential pairs (8 mil trace / 6 mil space typical) and keep digital outputs at least 5 mm away from the analog input traces.
The analog 1.8V AVDD and the digital 1.8V OVDD supplies should be generated from separate low-noise LDOs such as an LT3042 for AVDD (0.8 uVrms noise) and a separate LT3042 or LT3045 branch for OVDD to break ground-loop noise coupling. Bulk-decoupling 4.7 uF X7R ceramics should sit within 3 mm of each AVDD pin, bypassed by a 0.1 uF X7R within 1 mm for HF decoupling. Estimated: the part draws around 90 mA per AVDD1.8 supply at 25 Msps with both channels active; designers should budget for 130 mA (peak) and confirm headroom for the LVDS output drivers on OVDD.
Three common pitfalls with this ADC: (1) Forgetting to enable the internal LVDS 100-ohm termination (via the LVDS_TERM pin) when the trace is short, causing impedance mismatch and degraded bit-error rate; (2) Driving the analog inputs single-ended into one half of the differential pair instead of using a true differential driver like the AD8139 - this loses 6-10 dB of SFDR; (3) Not strobing the RESET pin after power-up to initialize the internal calibration register map, leading to intermittent gain drift. Designers should also ground the unused NC pins on the package rather than leave them floating to avoid field-coupling into AVDD1.8.
The serial LVDS outputs operate at up to 525 Mbps in 1-bit mode and benefit from internal termination (LVDS_TERM = high) for traces up to 5 cm. For longer traces, switch to external 100-ohm termination and disable internal termination. Estimated: at 25 Msps with 16-bit data and 1-bit serial mode, each LVDS lane toggles at 400 Mbps, requiring PCB dielectric material with loss-tangent less than 0.005 (FR4-grade 370HR is acceptable for 5 cm or shorter). Route LVDS lanes over a continuous ground plane with no splits and stitch ground vias every 25 mm for return-current continuity.
규정 준수 정보
RoHS compliant per Analog Devices product page (part number suffix #PBF indicates lead-free). AEC-Q100 not applicable for commercial-grade ADC; the LTC2190IUKG (industrial-grade, suffix I) covers -40C to +85C operation. Halogen-free status not stated in web data - mark unknown.
